Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

[Altera_Forum]

Hi,  

 Forgive me if the question is basic. I am new to the field of FPGAs.  I give a short version of the question. And a long version of the question. For those interested :).  Note: Requirement is Rx only. No Tx. Half the problem doesn't exist. All pins discussed below are with reference to input pins. :)  Short version: CML and LVDS are two high-speed differential signaling standards.  FGPA Development Kit 1 has pins on a port supporting CML differential I/O according to the kit reference manual.  The actual FPGA on the Development Kit supports LVDS on those pins according to the FPGA manual.  But the reference manual of the Dev Kit doesn't indicate support of LVDS on that port.  Is it possible to configure the actual pins of the FPGA to take an LVDS input instead of CML.  Long version:  Altera Stratix V DSP Development Kit. (Supports CML and LVDS on PortA)   connected to Altera Stratix III Development Kit. (Supports LVDS only)   Basically we want more LVDS lines on the Stratix V to receive input from the DE3 on a wider bus between the FPGAs. So looking for additional pins. Port A of the KIT has CML Rx receivers that could be configured as LVDS on the FPGA. Port B of the KIT has some differential DQS compatible pins that could be configured as LVDS on the FPGA.  In both cases, the reference manual of the kit does not indicate that the pins on the port are compatible to LVDS. The FPGA itself supports LVDS input according to the device handbook.  The connecter and cable between the boards will be based around Samtec EPLSP   A possible work around would be AC coupling between CML/LVDS Using an IC by TI sn65cml100  I'd like some guidance on going about such a task and whether its possible or not?  Cheers. Thanks for reading till here.  - Zubair  p.s. I can't post real hyperlinks cause I just joined the forum. I had links pasted in at every statement pointing to pdfs ..

[Altera_Forum]

--- Quote Start ---  It was actually wonderful of you to throw some ideas. Throughout our brainstorming sessions, none of us found out about the upcoming JEDEC standard..  Thanks for the heads up. Embedding the frame clock within the signal could be tricky in that case.  Lets hope the IC manufacturers handle these issues. The main benefit of using ADCs designed for a specific purpose is this. They cater the common configurations and problems faced in that specifc application within the IC. Like the phase shifts you mention.  Vendors usually cater for common clocks and daisy chain configurations of IC's which ensures (to a reasonable extent of accuracy) the phase margins between the signals.  AD9671, an 8-channel ADC for Ultrasound applications is coming soon. The preview page shows : "the ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface."  The DE3(Stratix III) does not have any transceivers. Would have simplified a lot of things if it did..  Thanks, Zubair  --- Quote End ---    Hello,   Why didn't you think about Linera Tech's LTM9010/9009/9011?