Using DDR3 memory without hard processor

[DP7]

Hi,

I have Cyclone V E 5CEFA9F23C7.

I need to sample ADC at very high speed (500MHZ) and stream it into an external DDR3 memory.

I connected a clock and memory controller in the qsys.

exported the files.

I dont know any idea how to use the momory.

what is the next step?

do i need an nios? is it a must?

how from here, and the instaniation i have from the qsys system, do i drive incoming data to the DDR?

[NurAida_A_Intel]

​ Hi DP7,

For Cyclone V, the maximum speed you can achieve on interface is 400 MHz. The fabric interface supports frequencies in the range of 10 MHz to one-half of the memory interface frequency. For example, for an interface running at 400 MHz, the maximum user logic frequency is 200 MHz. So, it is impossible to sample ADC at 500MHz as the maximum it can go is up to 200 Mhz and I am really sorry for the inconvenience caused. This information covered in EMIF estimator.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

The memory controller access using Avalon Memory-Mapped (AVMM) Interface as long as the logic/master component comply with the AVMM specification. For the timing diagram and AVMM specification, you can refer to Avalon Interface specifications. For Avalon Memory-Mapped Interface, you can refer to this chapter.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#page=12

You can see on this chapter, it explain the details of each avalon mm signals and there is timing diagram for clearer understanding.

Hope this helps.

[DP7]

First, thank you for the answer.

Now let put aside the sample rate i mentioned.

I just cant seem to figure what my next step should be - how to stream data to DDR3 memory.

What do i need to do? do i have to have a nios soft processor?

I am really looking for a very simple tutorial or example because i am really stuck on how to interface with the memory.

[NurAida_A_Intel]

​ Hi DP7,

It is not necessarily to use the nios as the memory controller access using the AVMM interface. To generate the example design and run simulation, refer to this chapter 13.3 (Uni-PHY Based Example Design) of the external memory hadbook:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf#page=406

On the simulation, you can check the traffic pattern of the avalon mm interface.

Hope this helps.

[DP7]

I am looking for some more detailed example.

a really step by step ( showing the qsys modules needed, explaining them, showing the hdl code)...

If you (or anyone else happens to know) any source for a beginner with all the DDR topics, as i mostly dealt with CPLD till recently

[sstrell]

As mentioned, you should try generating the example design from the IP parameter editor first, and work with that design to get an idea of how everything should work.

You can also check out this online training. It's older, but still completely applicable:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1110.html