FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5288 Discussions

Using PLL in the DE NANO Board

Altera_Forum
Honored Contributor II
964 Views

Hallo  

 

I have a DE0-NANO board and i found out from the specification that the board has a 50 MHz clock and the FPGA in the board can support upto 200 MHz of input clock. I also understood that to change the board clock frequency i need to use one of the on board PLL. 

 

I am developing my design in MATLAB and Simulink and then using the HDL coder to generate VHDL project, with all the necessary files. Then i put this project file in Quatras II software and want to download in the DE NANO board using the USB blaster. I am using a basic SDC file for timing constrains, and i need my design to run at 30 MHz for now. PLL comes from the ALTERA Mega core function library, my question is how can i add a pll to my design if i follow this steps? 

 

The other idea could be to do the whole process from MATLAB HDL coder, but the DE NANO board is not supported by my version of MATLAB, so i have to create a custom board then try to work on from there.
0 Kudos
0 Replies
Reply