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Using the SDRAM on the DE2-115 without NIOS, only HDL language

Altera_Forum
Honored Contributor II
1,335 Views

Hello, 

 

I am currently trying to implement a dual-port RAM in the DE2-115 evaluation board, using the 2x64 MB SDRAM chips. I do not want to use NIOS or SOPC builder at all, only using HDL language. 

 

At first I thought that the Altera Megafunction where suppose to do it but since there was no pin assignment to do I got sceptical and then understood that is was for the memory block of the Cyclone IV chip. 

 

 

Then I took a look at the datasheet of the SDRAM chip and also at the Quartus II handbook about the HDL coding style while interfering with memory modules but I am confused with all the different commands and operation that needs to be done to use the SDRAM (compared to a simple SRAM for example). 

As I already lost too many times already, I am wondering if somebody knows where I can find somekind of manual/tutorial, like the following link: ftp://ftp.altera.com/up/pub/altera_material/9.1/tutorials/vhdl/de2-115/using_the_sdram.pdf but without NIOS processor as I don't want to use it. 

 

 

Or in the worse case where I would need to do everything myself, is there some tips that needs to be known while using SDRAM or should I just apply "stupidly" the truth table of the SDRAM pins for the required operation (read/write)? 

 

Thank you in advance, 

 

 

Meach
0 Kudos
12 Replies
Altera_Forum
Honored Contributor II
258 Views

If You don't understand the way SDRAM works - the only solution to Your problem is memory megacore. It does all the required precharge/read/write stuff, so read the docu and it will be much easier to work. Also check the reference designs how SDRAM pins are constrained. Usually, MegaWizard generates a script which does all the job for constraints, You just need to specify locations.

Altera_Forum
Honored Contributor II
258 Views

Hi there, 

 

I'm currently stucked in the same problem, I'm trying to use the SDRAM of my DE2-115.  

my first try has been reading datasheet and doing my own controller, but is a mess. 

 

I understand the way sdram works, but I'm geting mad with the vhdl programation, is there a vhdl example or tutorial? 

 

Also, if use megacore, wich one is the one I need? because i tried two of them and i was unsuccessful tu make it work, I discard all the DDR (is this ok?) the issi sdram isn't a DDR 

 

Thanks, 

Guillermo
Altera_Forum
Honored Contributor II
258 Views

That ISSI chip isn't SDRAM chip at all. Not even talk about DDR SDRAM. Its SRAM, so You don't need any SDRAM controllers for that!

Altera_Forum
Honored Contributor II
258 Views

Issi is42s16320B datasheet says it's a 512Mbit Synchronous DRAM, 

 

there is an issi sram also, but I'm not interested in sram
Altera_Forum
Honored Contributor II
258 Views

My bad then, Altera usually used only SRAM chips by ISSI.

Altera_Forum
Honored Contributor II
258 Views

Hi taquionbcn, 

 

You can check on opencores (http://opencores.org/), there are some SDRAM controller in VHDL which are configurable. 

 

Meach
Altera_Forum
Honored Contributor II
258 Views

Meach, 

 

Which core did you end up using for your project? Did you use an Altera core, write one yourself, or use something else? Opencores?
Altera_Forum
Honored Contributor II
258 Views

What do you need the SRAM for? Please note, that the DE2-115 has both SDRAM and SRAM. 

SRAM reqires a straight forward memory mapped interface (only).
Altera_Forum
Honored Contributor II
258 Views

I'd like to revive this page. Someone might have new answers about this. I've just realized that the SDRAM in DE2-115 is not a DDR one so none in the MegaWizard IP works.  

 

In this tutorial, the SDRAM was used along side NIOS. I don't want to use NIOS like the thread starter. ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/vhdl/de2-115/using_the_sdram.pdf 

 

Any insights on how to implement the SDRAM without NIOS?  

 

In Chapter 9: Implementing and Parameterizing Memory IP 9–3 Design Flow of this handbook (http://www.altera.com/literature/hb/external-memory/emi_plan.pdf), it showed two possible ways to generate the IP. One using the Qsys and the other using the MegaWizard. Can someone share their knowledge on how to create a complete IP of the SDRAM Controller using Qsys with AVALON interface as the controlling component?
Altera_Forum
Honored Contributor II
258 Views

You might try starting with an example that uses NIOS. Then remove the NIOS and drive the SDRAM controller directly.

Altera_Forum
Honored Contributor II
258 Views

Better use small Nios and use DMA as You will still need to pass the initialization.

Altera_Forum
Honored Contributor II
258 Views

 

--- Quote Start ---  

I'd like to revive this page. Someone might have new answers about this. I've just realized that the SDRAM in DE2-115 is not a DDR one so none in the MegaWizard IP works.  

 

In this tutorial, the SDRAM was used along side NIOS. I don't want to use NIOS like the thread starter. ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/vhdl/de2-115/using_the_sdram.pdf 

 

Any insights on how to implement the SDRAM without NIOS?  

 

In Chapter 9: Implementing and Parameterizing Memory IP 9–3 Design Flow of this handbook (http://www.altera.com/literature/hb/external-memory/emi_plan.pdf), it showed two possible ways to generate the IP. One using the Qsys and the other using the MegaWizard. Can someone share their knowledge on how to create a complete IP of the SDRAM Controller using Qsys with AVALON interface as the controlling component? 

--- Quote End ---  

 

 

I am trying to do the same for distributed processing. The ISSI chip on the DE2-115 is Single Data Rate (SDR) SDRAM. There is an SDRAM Controller available from the IP Catalog under the following in Qsys: 

Memory Interfaces with ALTMEMPHY>SDRAM>SDRAM Controller. 

 

You would then export the signals to the external RAM chip and connect the in/outputs in your toplevel VHDL or Verilog file. To interface with the chip, you would have to adhere to the Avalon-Memory Mapped interface specification, which is standard and would be the same way you would interact with on-chip memory (See the Avalon Interface Specificaitons document or look for some examples).  

 

One thing that you must remember is that the SDRAM chip clock DRAM_CLK leads the system clock CLK_50 by 3 nanoseconds on the DE2-115. You may have to include a Phase Lock Loop (PLL) module to adjust for the offset. This is described when interfacing with the Nios II and should hold for custom logic as well due to off-chip latency. Hope that works! 

 

The document "Using the SDRAM on Altera’sDE2-115 Board" has that timing detail as well as an example with the Nios II as reference. 

 

(please rep if you find helpful =)
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