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VID settings for Stratix 10 GX development kit.

HEass1
Beginner
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Hi,

 

I am trying to compile my own design into a Stratix 10 GX development kit and I keep getting an error that the VID settings are not complete. I searched the web and found information for the Stratix 10 MX dev. kit, but does anyone know what the correct ones are for the GX kit? Of course I could try using the same ones, but I would rather get the official answer, given that we're talking about power control.

 

Thanks.

MX_board_settings.PNG

 

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AR_A_Intel
Employee
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Hello,

 

Welcome to INTEL forum. VID is basically will be different from board to board depends on the on-board power regulator design.

For your case, the easier way is to refer to S10 GX dev kit reference design, and check out the VID setting in reference design Quartus design and *.qsf file

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html

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HEass1
Beginner
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Thanks, but there is only one qsf in the software package for the GX dev kit (s10_fpga_golden_top.qsf) and it does not have those settings in it. I started with that qsf for my own design and still got these errors.

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AR_A_Intel
Employee
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Hi Sir

 

Upon checking with team members, S10 GX dev kit do not provide VID setting in reference design. From my findings, VID setting is provided in Intel Stratix 10 TX SI Development Kit https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kits-s10-tx-si.html

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HEass1
Beginner
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Thanks. I checked the settings for the TX board and modified them to fit the GX board and now it works(!). I used:

 

PWRMGT_works.PNG

Thanks again.

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AR_A_Intel
Employee
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Good to know it help and thanks for informing

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