VREFB<#>N0 pin A and vccio on MAX10

[MartinMaa]

HI, 

VREFB<#>N0 pin and VCCIO differ in what aspects?
What is the purpose of using VREFB<#>N0?

I have read the documentation, but I still do not understand the explanation about VREFB in the document.

Thanks

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[FvM]

Hi,
is the explanation in Pin Connection Guidelines unclear in any regard?

VREFB<#>N0
These pins are dual-purpose pins. For Banks 1A and 1B, VREF pins are shared.

Input reference voltage for each I/O bank. If a bank uses a voltage referenced I/O standard for input operation, then these pins are used as the voltage-reference pins for the bank.

If you are not using the VREF pins in banks or shared banks, connect unused pins as defined in the Intel Quartus Prime software.
When VREF pins are used as I/O pins, they have higher capacitance than regular I/O pins which will slow the edge rates and affect I/O timing.

Are you using voltage referenced I/O standard? 

[MartinMaa]

Thank you for your response.

My confusion lies with the VREF pins. What is their intended purpose when I use them?

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[MartinMaa]

HI,

Is it intended for ADC and DAC-related applications?

[FvM]

No, as quoted, it's for voltage referenced IO standards, particularly DDR-RAM interfaces. Review the respective chapter about IO.

[MartinMaa]

Hi,  How does the intended use of VREF differ from that of VCCIO voltage?

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[FvM]

Instead of repeating unelaborated questions you should review device manual about intended usage of VREFB pins for voltage refernced IO standards. Usually they are biased at VCCIO/2, defining the input threshold.

[AqidAyman_Intel]

Hi,

As mentioned by @FvM, Vref pin is different from VCCIO pin where VCCIO pin is applicable for all I/O banks because it is for the bank power supply. However, for Vref pin, it is a reference voltage for certain I/O standards which include SSTL, HSUL and HSTL I/O standards in Intel Max 10.

Voltage referenced I/O standards: https://www.intel.com/content/www/us/en/docs/programmable/683794/current/single-ended-sstl-hstl-and-hsul-i-o-24395.html

[MartinMaa]

Hi,

Do we need to set VREF for TTL level?

If yes, what is the approximate voltage value?

I am planning to use the MAX10 as a FIFO, with the MAX10 input connected to the output of MT9P001, and the MAX10 output connected to the input of CYUSB3014.

Thanks,

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[AqidAyman_Intel]

There is no TTL in the listed I/O standard of the Max 10.

For the reference of FIFO IP core in Intel Max 10, you can refer below link:

https://www.intel.com/content/www/us/en/docs/programmable/683431/current/fifo-ip-core-references.html

[MartinMaa]

Hi, Thank you for this link.

My problem is that Should I connect VREF PIN  to voltage , If I use TTL logic?

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[MartinMaa]

Hi, I would like to ask if this means NC. Besides enabling VREF NC, do I need to make any additional settings, such as FPGE firmware?

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[AqidAyman_Intel]

HI,

You can refer to the link below on the list of I/O standards supported in Intel Max 10. You can refer either it is voltage referenced I/O standard or not under "Type" column. If it shown as "voltage-referenced", means you need to connect Vref pin to voltage.

https://www.intel.com/content/www/us/en/docs/programmable/683751/22-1/i-o-standards-support.html

For the single-ended I/O standard, you no need to connect the Vref pin to voltage. Based on the Pin Connection Guidelines, which you can refer to below link, if you are not using the VREF pins, you can connect unused pins as defined in the Intel® Quartus® Prime software.

https://www.intel.com/content/www/us/en/docs/programmable/683232/current/differential-i-o-pins.html

For the unused pin settings in Intel Quartus software, you can refer below link:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#comp/comp/comp_tab_dp_unused_pins.htm