I am doing a design with MAX10 FPGA (10M25DAF484I). I am using both the internal ADC IPs and i have connected the ADC_VREF pin to a reference 2.5V power supply.
Right now i have not connected VREFB1N0, VREFB2N0, VREFB3N0, VREFB4N0, ...VREFB8N0. Can i leave all the VREFB<#>N0 pins unconnected? Or what should be the recommended connectivity?
The connection guidelines document says that: "If you are not using the VREF pins in banks or shared banks, connect unused pins as defined in the Intel Quartus Prime software" But i don't have any Quartus software installed to check.
I need to freeze on the hardware quickly. So please reply.
Hello, I have the same questions about these pins.
What is the purpose of these pins, what are the signal specifications,
and when are these pins required?
How can voltage be applied to these pins?
If these pins are not in use, how should they be handled?
Thank you for your response.