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Altera_Forum
Honored Contributor I
765 Views

Verilog delays~?

Hello, I'm writing a verilog prog on my DE1 to read off the flash memory... but I cannot 

figure out how I can wait until the read completes before continuing in my program. 

 

I set f_read = 1 outside to allow the read to begin 

we set f_busy = 1 during this time. 

After 1 ms, we finish up and reset the registers 

 

 

|| //50MHz = 20 ns/cycle  

|| always @(posedge CLOCK_50) begin 

|| if (f_read == 1) begin 

|| f_busy <= 1; 

||  

|| if (f_count == 0) begin 

||  

|| //set up signals here 

||  

|| //wait 0.2 ms 

|| end else if(f_count == 1) begin 

||  

|| //data is now valid, store it 

||  

|| //wait 1 ms 

|| end else if(f_count == 5) begin 

||  

|| f_count <= 0; //reset stuff 

|| f_busy <= 0;  

|| end 

||  

|| if(f_busy == 1) begin 

|| f_count <= f_count+1; 

|| end 

|| end 

|| end 

 

So, say I have a task called read_flash. We set f_read in here - what can I put in there to wait for f_busy to equal 0?
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5 Replies
Altera_Forum
Honored Contributor I
68 Views

So I built this... but.... 

 

always @(posedge read_flash_pixel or posedge flash_pause_done) begin 

if (read_flash_pixel) begin 

flash_pause <= 1; 

end else begin 

flash_pause <= 0; 

end 

end 

 

always @(posedge CLOCK_50) begin 

if(flash_pause == 1) begin 

flash_pause_count <= flash_pause_count+1;  

 

if (flash_pause_count == 1) begin 

mod_pixel_addr <= pixel_addr; 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 5) begin 

pixel_p1 <= save_data; 

mod_pixel_addr <= (pixel_addr+1'b1); 

 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 10) begin 

pixel_p2 <= save_data; 

mod_pixel_addr <= (pixel_addr+2'b10); 

 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 15) begin 

pixel_p3 <= save_data; 

flash_pause_done <= 1; 

read_flash <= 0; 

end  

end else begin 

flash_pause_count <= 0; 

end 

 

flash_pause_done <= 0; 

end 

 

I get a latch warning here... and... 

 

Error (10200): Verilog HDL Conditional Statement error at RealTime2.v(264): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct 

 

 

always @(posedge read_flash or posedge f_done) begin 

//trigger read 

if (read_flash == 1) begin 

data_addr <= mod_pixel_addr; 

f_read <= 1; 

end else begin 

f_read <= 0; 

end 

end
Altera_Forum
Honored Contributor I
68 Views

 

--- Quote Start ---  

So I built this... but.... 

 

always @(posedge read_flash_pixel or posedge flash_pause_done) begin 

if (read_flash_pixel) begin 

flash_pause <= 1; 

end else begin 

flash_pause <= 0; 

end 

end 

 

always @(posedge CLOCK_50) begin 

if(flash_pause == 1) begin 

flash_pause_count <= flash_pause_count+1;  

 

if (flash_pause_count == 1) begin 

mod_pixel_addr <= pixel_addr; 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 5) begin 

pixel_p1 <= save_data; 

mod_pixel_addr <= (pixel_addr+1'b1); 

 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 10) begin 

pixel_p2 <= save_data; 

mod_pixel_addr <= (pixel_addr+2'b10); 

 

read_flash <= 0; 

read_flash <= 1; 

 

end if (flash_pause_count == 15) begin 

pixel_p3 <= save_data; 

flash_pause_done <= 1; 

read_flash <= 0; 

end  

end else begin 

flash_pause_count <= 0; 

end 

 

flash_pause_done <= 0; 

end 

 

I get a latch warning here... and... 

 

Error (10200): Verilog HDL Conditional Statement error at RealTime2.v(264): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct 

 

 

always @(posedge read_flash or posedge f_done) begin 

//trigger read 

if (read_flash == 1) begin 

data_addr <= mod_pixel_addr; 

f_read <= 1; 

end else begin 

f_read <= 0; 

end 

end 

--- Quote End ---  

 

 

Hi, 

 

you have to define what should happend to "data_adder" in the else branch. 

 

Kind regards 

 

GPL
Altera_Forum
Honored Contributor I
68 Views

I'm not a Verilog expert, but I think your problem is with this line: 

always @(posedge read_flash_pixel or posedge flash_pause_done)  

 

First of all you have two clocks driving the same process, and this is not a good coding practice.  

Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this. 

 

I'd use the always @(posedge CLOCK_50) for this process, too. 

Every clock cycle you can store read_flash_pixel and flash_pause_done levels and in the next one you test the edge condition.
Altera_Forum
Honored Contributor I
68 Views

Cool! I ended up using the negedge CLOCK_50 so it gets done before the next clock cycle on the next step of the setup :-) that seems to work nicely :D

Altera_Forum
Honored Contributor I
68 Views

 

--- Quote Start ---  

I'm not a Verilog expert, but I think your problem is with this line: 

 

always @(posedge read_flash_pixel or posedge flash_pause_done) 

 

First of all you have two clocks driving the same process, and this is not a good coding practice. Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this. 

--- Quote End ---  

 

 

To clarify this point. It's legal Verilog syntax, not involving two clocks. But I guess, it's not what the original poster wanted, he may have misunderstood this common Verilog construct himself. 

 

read_flash_pixel is not a clock, if it's used together with if (read_flash == 1), it's an asynchronous input. The respective VHDL code is 

process(read_flash_pixel , posedge f_done); begin if read_flash_pixel = '1' then -- elsif rising_edge(posedge f_done) then -- end if; end process; 

I think, it's useful to know the basic constructs of a "foreign" language, otherwise you can't read the code.
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