FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
5547 Discussions

Very unstable JTAG chain on PCI Express Development Kit, Stratix II GX Edition

Altera_Forum
Honored Contributor II
1,001 Views

We have such board: "PCI Express Development Kit, Stratix II GX Edition", 

http://www.altera.com/products/devkits/altera/kit-pciexpress_s2gx.html 

It contains EP2SGX90 and EPM570 devices on the same JTAG chain. They are also claimed as multi-voltage. 

Programming is very unstable (by Quartus programmer). Sometimes it detects two devices, sometimes it even program both, but often says "Error: Can't access JTAG chain", sometimes also "Error: CONF_DONE pin failed to go high in device 2". 

Nios II IDE also cannot load anything inside Nios II CPU. 

Is this JTAG unstability is connected somehow with multi-voltage feature? 

USB Blaster is used, BTW. 

Is there any special DIP configuration need to be set?
0 Kudos
0 Replies
Reply