FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.
5848 Discussions

We are using CycloneIII EP3C55 FPGA, With configuration flash of EPCS16. We want to perform timing analysis for writing of data from FPGA to Flash. I want the DCLK to Serial data out delay for the FPGA.

RMath11
Beginner
530 Views
 
0 Kudos
3 Replies
YuanLi_S_Intel
Employee
281 Views

Hi Rajaram,

 

May i know what is the reason to delay the DCLK? Are you connecting the flash memory device with 2 FPGA? Please clarify.

 

Regards,

YL

0 Kudos
RMath11
Beginner
281 Views

Hi YL,

I am not delaying the DCLK,

I want the time delay between DCLK and Valid data given out by FPGA.

 

Thanks,

Raja

 

0 Kudos
YuanLi_S_Intel
Employee
281 Views

Hi Raja,

 

Thanks for the clarification. If you are looking for the delay for configuration pin. You may refer to datasheet at link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf (Page 17)

 

Regards,

YL

0 Kudos
Reply