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Hi Rajaram,
May i know what is the reason to delay the DCLK? Are you connecting the flash memory device with 2 FPGA? Please clarify.
Regards,
YL
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Hi YL,
I am not delaying the DCLK,
I want the time delay between DCLK and Valid data given out by FPGA.
Thanks,
Raja
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Hi Raja,
Thanks for the clarification. If you are looking for the delay for configuration pin. You may refer to datasheet at link below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf (Page 17)
Regards,
YL

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