Here are the requirements base on our compiler results:
- Family - ACEX1K
- Device - EP1K100QC208-1
- Timing Models - Final
- Met timing requirements - Yes
- Total logic elements - 2,440 / 4,992 ( 49 % )
- Total pins - 132 / 147 ( 90 % )
- Total memory bits - 23,808 / 49,152 ( 48 % )
- Total PLLs - 0 / 1 ( 0 % )
We will be revising the PCB to accommodate the new FPGA, but we'd like to use the same FPGA firmware if possible with minimal software development required.
When you mention software, do you mean using NIOS(c code) or just verilog or vhdl code?
Yes, you are right, Max 10 had more LE compare to Max V. You may also consider other device depending on your requirement. You can check over here.
We're using Quartus II 9.0sp2 Web Edition. There is very little custom code and most of the design is using the MegaWizard Plug-Ins. I reviewed the other FPGAs and the MAX 10 and Cyclone 10 seem like the best fit. The Cyclone 10 has a lot more LEs and more capability that we currently require, but might be a good fit for our next generation product which we will be developing in the next couple of years. Right now our requirement is a direct replacement for the design based on the ACEX 1K.