FPGA, SoC, And CPLD Boards And Kits
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What is JP3 on the DE1 Development Board

Altera_Forum
Honored Contributor II
‎06-10-2008 07:04 PM
1,180 Views

Hi There, 

After having a close look at my DE1 I noticed there is an un-populated header on the board titled JP3 in the USB blaster area. 

I also checked the schematics and JP3 also has the title "CPLD ISP". 

Could I use this to program other boards with the DE1's USB blaster or is this a port for programming the MAX chip on the DE1 from an external USB blaster? 

 

its its the latter, is there any way of tapping into the DE1's USB blaster to use it as a stand-alone USB blaster? 

 

thanks
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Altera_Forum
Honored Contributor II
‎06-10-2008 08:04 PM
520 Views

 

--- Quote Start ---  

Could I use this to program other boards with the DE1's USB blaster or is this a port for programming the MAX chip on the DE1 from an external USB blaster? 

--- Quote End ---  

Its for production programming of CPLD and USB EEPROM.
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