I have developed a minimal solution for receiving and transmitting ethernet frames with the cyclone10lp evaluation kit and now I am designing a test card with gigabit ethernet with minimal pcb footprint.
At the moment I am only using the 12 rgmii signals and mdio/mclock needed for mdio. I would like to have the bare minimal circuit for operating the phy for minimal footprint.
Can I leave out
- leds, I am using the fpga and I can read all of the necessary information from the mdio registers
- bootstrap resistors as with mdio, I do not care about the configuration at boot
- enet xtal, if I am using a clock output from the fpga as the phy clock
- jtag circuit, can these be left open, if I am not interested in using jtag directly at the phy?
I crossed out the circuits I would like to leave out on the PDF, which shows the phy connection page from the evaluation kit schematic.
Also, what kind of accuracy is required from the length matching between pairs of differential traces between phy and magnetics and by extension between magnetics and connector. Just by observing the evaluation kit circuit it seems that the traces are not length matched between TPIDN/TPIDP and TPIAN/TPIAP.
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I am sorry to inform you that Intel FPGA doesn't provide board design consultation to customer. Board design is out of our support capability as well. The closest that we can do is to share with you Intel FPGA dev kit board as reference which you already have.
Anyway, this is forum community. Let's see if there is board design expert that can jump into forum discussion to help you out here.