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What is the appropriate way to specify the SDC for "..was determined to be a clock but was found without an associated clock assignment."

TNine
Beginner
839 Views

I already read https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an545.pdf?language=en_US

 

and

 

https://forums.intel.com/s/question/0D50P00003yyHQNSA2/diagnosing-signal-was-determined-to-be-a-cloc...

 

but I could not find the answer.

I have an sdc where I define

 

create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]

create_clock -name "enc_a" -period 20.000ns [get_ports {enc_a}]

set_clock_groups -asynchronous -group {CLOCK_50} -group {enc_a}

where CLOCK_50 is my main clock and enc_a is a signal from an encoder.

 

I syncrhonize the enc_a end enc_b using

assign clk=CLOCK_50; always @(posedge clk) begin {metaA,metaB}<={enc_a,enc_b}; {stableA,stableB}<={metaA,metaB}; end   rotaryEncoder rotaryEncoder(.a(stableA),.b(stableB),.reset(reset),.q(stableQ));  

 

 

where rotaryEncoder is the following module

 

module rotaryEncoder(a,b,reset,q);   input a,b,reset; output reg [31:0] q; always @(posedge a,posedge reset) begin if (reset) begin q<=32'h0; end else if (b) begin q<=q+32'h1; end else begin q<=q-32'h1; end end endmodule

However I get the message

 

Warning (332060): Node: busRotaryEncoder:busRotaryEncoder|stableA was determined to be a clock but was found without an associated clock assignment.

Info (13166): Register busRotaryEncoder:busRotaryEncoder|rotaryEncoder:rotaryEncoder|q[5] is being clocked by busRotaryEncoder:busRotaryEncoder|stableA

 

To my understanding, the "set_clock_groups -asynchronous" should solve the problem, but it seems not. How should I specify this situation in the sdc file?

0 Kudos
3 Replies
sstrell
Honored Contributor III
222 Views

You set signal a (aka stableA) as a new clock domain for the rotaryEncoder, so it must be constrained with a generated clock constraint. stableA is based off metaA and metaA is based off enc_a, so metaA is a generated clock as well. Something like this would work:

 

create_generated_clock -source [get_ports enc_a] -multiply_by 1 [get_pins <register that creates metaA>|q] -name metaA

create_generated_clock -source [get_pins <register that creates metaA>|q] -multiply_by 1 [get_pins <register that creates stableA>|q] -name stableA

 

The set_clock_groups command only prevents analysis for data transfers between the two clock domains you mention. It does not constrain the clock that drives the rotaryEncoder.

 

#iwork4intel

 

TNine
Beginner
222 Views

Thank you very much, and sorry for the late reply. I could not make it work with get_pins, and switched to get_nodes. This is how the sdc now reads:

 

create_generated_clock -source [get_ports enc_a] -multiply_by 1 [get_nodes {busRotaryEncoder:busRotaryEncoder|metaA}] -name metaA   create_generated_clock -source [get_nodes {busRotaryEncoder:busRotaryEncoder|metaA} ] -multiply_by 1 [get_nodes {busRotaryEncoder:busRotaryEncoder|stableA}] -name stableA

However I get a new warning.

 

Warning (332088): No paths exist between clock target "busRotaryEncoder:busRotaryEncoder|metaA" of clock "metaA" and its clock source. Assuming zero source clock latency.   Warning (332088): No paths exist between clock target "busRotaryEncoder:busRotaryEncoder|stableA" of clock "stableA" and its clock source. Assuming zero source clock latency.  

 

Why does quartus detect no path even if there is the above mentioned synchronization?

 

GuaBin_N_Intel
Employee
222 Views
I think TQ did not expect any feedback clock in your implementation and gave the warning https://www.intel.com/content/www/us/en/programmable/quartushelp/18.0/index.htm#msgs/msgs/wsta_no_va...
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