What is the series of register WRs and RDs that must be done to activate the 10G Ethernet? Is there an example of using the MAC, PHY layers to activate the 10G port?

[AGeie1]

Just what are the registers i need to write to and the bits, and any reads to setup the 10G port to become active with a host computer connection.

[AlfredoS_Intel]

Hi Ageie1,

Thank you for posting in our Intel® Ethernet Communities Page.

Please provide us the model of the ethernet card that you want these registers for.

Kindly also provide us a background and the reason why you need to get the information.

We look forward to hearing from you. If we do not get your reply, we will follow up after 3 business days.

Best Regards,

Alfred S

Intel® Customer Support 

[AGeie1]

This is to activate the 10G SPF port on the Alteria 10 Arria Development Kit Board. What is the sequence of setting up the 10Gig E port. Activating through software. Which registers will give me a basic operation. I constructed a 1G FPGA and activated the FPGA 1G ethernet with a few writes to address in MAC, MDIO and i could construct a ethernet packet in FIFO and transmit to a host computer. I like to do the same with 10Gig E, but am having a problem doing so, i cannot get the data in FIFO to transmit over the port. Undoubtedly i am not setting up something correctly to activate the port as i did with the 1G FPGA port.

Thanks

Ardie 

[AlfredoS_Intel]

Hi AGeie1,

Thank you for providing more information regarding your issue.

We have a dedicated forum for your concern.

So you will be better assisted, we will transfer your thread to the correct channel.

Thank you for reaching out in our Intel® Ethernet Communities page.

Best Regards,

Alfred S

Intel® Customer Support

[SengKok_L_Intel]

Hi,

This is to let you know that this community page is just transferred to the Intel FPGA support team.

For Arria 10 Low Latency Ethernet MAC IP, the TX and RX paths are enabled by default,  there is no specific register that the user must initialize after power-up.

As for the example design, you may refer to the following user guide to generate the example design from the Low Latency Ethernet 10G MAC IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20016.pdf

Thank you.

Regards -SK

[SengKok_L_Intel]

Hi,

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards -SK