Question about LVDS implementation with external PLL.
We are using 10M50 board. Since there is no LVDS tx output clock when using external PLL, how does Rx end recover the data it received through Serdes link? How is Rx end deal with phase change without DPA?
Kindly find the explanation with using external PLL when using LVDS tx output
If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core: • Serial clock input to the tx_inclock port of the Altera Soft LVDS transmitter. • Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port
Reference page no: 21
what I mean is, on the other side of lvds, whose Rx receives this signal, how can it deal with the phase mismatch? Since Rx's clock is provided by its local PLL.
For example in the picture, board 1 send data with phase 1, and data is received by board 2. But board 2 has PLL clock with different phase 2.
How does Rx on board 2 sample this signal when phase are different?
The data realignment is done by using bit slip , there is a block known as data realignment block , for further reference kindly refer no:27 of the below document
I understand your concern, with my know knowledge the explanation for the data realignment is not there in the lvdsUG for Max 10. And I do not have any procedure , but in Stratix 10 UG , there is recommendations. May be you can implement the same in Max 10.
Refer page no:27