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Jiayi_H_Intel
Employee
207 Views

When LVDS using external PLL, how does Rx recover data and deal with phase changing?

Hi experts,​

Question about LVDS implementation with external PLL.

We are using 10M50 board. Since there is no LVDS tx output clock when using external PLL, how does Rx end recover the data it received through Serdes link? How is Rx end deal with phase change without DPA? 

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7 Replies
Rahul_S_Intel1
Employee
86 Views

Hi ,

Kindly find the explanation with using external PLL when using LVDS tx output

If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core: • Serial clock input to the tx_inclock port of the Altera Soft LVDS transmitter. • Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port

Reference page no: 21

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

Jiayi_H_Intel
Employee
86 Views

what I mean is, on the other side of lvds, whose Rx receives this signal, how can it deal with the phase mismatch? Since Rx's clock is provided by its local PLL.

For example in the picture, board 1 send data with phase 1, and data is received by board 2. But board 2 has PLL clock with different phase 2.

How does Rx on board 2 sample this signal when phase are different?

 

Picture2.png

Jiayi_H_Intel
Employee
86 Views

Rahul_S_Intel1
Employee
86 Views

Hi ,

The data realignment is done by using bit slip , there is a block known as data realignment block , for further reference kindly refer no:27 of the below document

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

Jiayi_H_Intel
Employee
86 Views

I am not asking about realignment, but phase recovery method without DPA.

Rahul_S_Intel1
Employee
86 Views

Hi ,

I understand your concern, with my know knowledge the explanation for the data realignment is not there in the lvdsUG for Max 10. And I do not have any procedure , but in Stratix 10 UG , there is recommendations. May be you can implement the same in Max 10.

Refer page no:27

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/archives/ug-s...

 

 

Rahul_S_Intel1
Employee
86 Views

Hi ,

Kindly let me know if you need further assistance

 

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