Where does channel data stored when the AXI interconnect is busy?

[efe373]

Assume the AXI interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the master itself or at the master/slave interface or at the AXI interconnect? I assume these signals coming from channels should be stored in some FIFOs. However, I do not know where are these FIFOs.

If it is a design-specific problem, how Intel implements it?

[aikeu]

Hi efe373,

This will depends on your overall design to determine how the FIFO is handled in your system.

I do not have a specific answer to your question.

Similar reference to the handling of FIFO can refer to chapter 2 and 24 of Embedded Peripherrals user IP guide.

Embedded Peripherrals user IP guide link:

https://d2pgu9s4sfmw1s.cloudfront.net/DITA-technical-publications/PROD/PSG/ug_embedded_ip-683130-670523.pdf?Expires=1641532629&Key-Pair-Id=APKAJKRNIMMSNYXST6UA&Signature=Oy1Lr6ISYy6ExGSP8d-NOl6fQv6DPz0S36QFfs6fEB4ars8suDcpSAUJh5YULOdvjP8G45po7vhwXkC9NCSnXWslW6C4K5SQZ2dy6BGX-7HYqi4qlrROTxDK9IodpYlkq490lsDKVdjFZcUAKvcSlpUJ6zno7T2vjmNzZa4940UaU0e7GIRH...

Thanks.

Regards,

Aik Eu

[aikeu]

Hi efe373,

I will close this thread if no further questions.

Thanks.

Regards,

Aik Eu