Assume the AXI interconnect is busy at the moment, and there is a master that wants to read/write something to a slave. So, is this request stored temporarily at the master itself or at the master/slave interface or at the AXI interconnect? I assume these signals coming from channels should be stored in some FIFOs. However, I do not know where are these FIFOs.
If it is a design-specific problem, how Intel implements it?
This will depends on your overall design to determine how the FIFO is handled in your system.
I do not have a specific answer to your question.
Similar reference to the handling of FIFO can refer to chapter 2 and 24 of Embedded Peripherrals user IP guide.
Embedded Peripherrals user IP guide link: