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BMart12
Beginner
158 Views

Where or how can I get import mgc_axi_pkg::* ?

Hello, I am using Quartus Prime 18.1.0 Standard Edition and ModelSim - Intel Starter Edition 10.5b. I am trying to simulate an HPS design I made on Platform Designer. The macro file fails to load because the above package is missing. The module soc_system_hps_0_fpga_interfaces.sv has the above import statement.

 

Thanks, Ben Martinez

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6 Replies
127 Views

Hi

The package is a part of mentor IP files

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/mentor_vip_ae_usr.pdf

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedd...

can you check and let us know , whether you are able to find files like mgc_common_axi.sv in your system.

Thanks and Regards

Anil

BMart12
Beginner
127 Views

Hi Anil,

 

Yes, I found the folder C:\intelFPGA_lite\18.1\ip\altera\mentor_vip_ae\axi3\bfm that has mgc_common_axi.sv and other mgc_axi* files.

 

Ben

127 Views

Hi ,

If you check the mgc_common_axi.sv , you should be seeing the package.

package mgc_axi_pkg;

Please check why it is not getting imported , please refer the system verilog guidelines and the scripts which are being used to debug the same.

Thanks and Regards

Anil

BMart12
Beginner
127 Views

Hi Anil, Below is the list of the files in the folder that contains mgc_axi* files. As you see, mgc_axi_pkg is missing. I edited the source file that is importing mgc_axi_pkg.sv to import mgc_axi_bfm_pkg.vhd. I encountered errors due to VHDL differences with Verilog. I am letting go of trying to simulate soc_system. You can close this case unless you can provide me with the missing package. Thanks for your help. Ben Volume in drive C is OS Volume Serial Number is 0AFB-B554 Directory of C:\intelFPGA_lite\18.1\ip\altera\mentor_vip_ae\axi3\bfm 06/16/2020 12:09 PM <DIR> . 06/16/2020 12:09 PM <DIR> .. 06/16/2020 12:09 PM 0 mgc.lst 02/20/2019 04:09 AM 290,692 mgc_axi_bfm_pkg.vhd 02/20/2019 04:09 AM 382 mgc_axi_inline_monitor.mti.svp 02/20/2019 04:09 AM 7,727 mgc_axi_inline_monitor.sv 02/20/2019 04:09 AM 13,034 mgc_axi_inline_monitor.vhd 02/20/2019 04:09 AM 14,996 mgc_axi_inline_monitor_hw.tcl 02/20/2019 04:09 AM 507 mgc_axi_master.mti.svp 02/20/2019 04:09 AM 100,722 mgc_axi_master.sv 02/20/2019 04:09 AM 28,778 mgc_axi_master.vhd 02/20/2019 04:09 AM 10,729 mgc_axi_master_hw.tcl 02/20/2019 04:09 AM 505 mgc_axi_monitor.mti.svp 02/20/2019 04:09 AM 96,028 mgc_axi_monitor.sv 02/20/2019 04:09 AM 34,501 mgc_axi_monitor.vhd 02/20/2019 04:09 AM 505 mgc_axi_slave.mti.svp 02/20/2019 04:09 AM 118,731 mgc_axi_slave.sv 02/20/2019 04:09 AM 34,681 mgc_axi_slave.vhd 02/20/2019 04:09 AM 11,648 mgc_axi_slave_hw.tcl 02/20/2019 04:09 AM 1,674,282 mgc_common_axi.sv 18 File(s) 2,438,448 bytes 2 Dir(s) 366,858,219,520 bytes free
127 Views

Hi

The package mgc_axi_pkg and its implementation is available inside the file mgc_common_axi.sv.

Thanks and Regards

Anil

BMart12
Beginner
127 Views

Hi Anil, I added the following line to the soc_system.do macro file I am using: vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_common_axi.sv} This inclusion required the following line to resolve “file not found” errors: vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd} The next error was for mgc_axi_bfm_pkg, I added the following line: vlog -work work +incdir+/home/bmartinez/JT/c5FPGA/JtF31C8_c {/home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd} As you can see, the missing package is written in VHDL. I next get the following errors: # ** Error: (vlog-13036) /home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd(1): near "--": Operator only allowed in SystemVerilog. # ** Error: (vlog-13069) /home/bmartinez/JT/c5FPGA/JtF31C8_c/soc_system/testbench/soc_system_tb/simulation/submodules/mgc_axi_bfm_pkg.vhd(1): near "--": syntax error, unexpected --, expecting class. # End time: 11:32:44 on Jun 17,2020, Elapsed time: 0:00:01 # Errors: 2, Warnings: 0 I need to research how to mix VHDL and Verilog for modelsim. I will add this task to my work queue. Thanks for your help. Ben