I created a NiosII design with some custom IPs. I used Platform designer to generate the tcl wrapper for those designs and integrated it inside the Nios.
Now, during the generation of the SoC design (niosii_core.vhd), the naming is right for the Synthesis (eg MyCore_0) whereas for the Simulation I get niosii_core_MyCore_0 as name. When launching the msim_setup.tcl and I run the simulation it tells me that obviously niosii_core_MyCore_0 cannot be bound.
I use a MAX10 FPGA with Quartus Lite 18.1 for Windows. Do you have any idea how to fix this issue ?