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Beginner
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Why is Quartus creating modules without valid VHDL/verilog identifiers?

I am attempting to build a project for the A10 soc development kit, and it fails and shows errors about not valid VHDL/verilog identifiers. Please see the attached screenshot.

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Hi,

 

May I know which edition and version of the software you are using? Kindly share the testcase for investigation.

 

Thanks.

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Hi,

 

Do you have any updates?

 

Thanks.

Best regards,

KhaiY

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