FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Why the SOF file fail to be programmed to FPGA with NIOS Design

CMetn
Beginner
598 Views

Hi,

This isn't the first time to program an FPGA. and it fail while downloading the sof file. without adding the NIOS design was working fine. Can you explain to me why, If you can....

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Ahmed_H_Intel1
Employee
307 Views

Hi,

Can you please check the JTAG configurations. mainly I am suspecting the JTAg speed.

And also check the cable you are using, if everything is correct. I am open to review your design if you are welling to share with us (Screen shots are just fine)

Regards,

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