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Will the weak pull ups on I/O prior to configuration damage other unpowered ICs it is connected to?

RDiva
Novice
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I am designing a cyclone IV device connecting to an ARM processor and DSP. On power up, there is some finite time before the ARM processor would configure the FPGA through passive serial method. The DSP has some signals wired to the FPGA. The DSP may remain in powered down mode until the FPGA is configured. Since the DSP I/O voltages aren't up and because the FPGA I/Os are in weak pull up state prior to configuration, can it damage the DSP pins? Or are weak pull-ups almost synonymous to tristate?

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SreekumarR_G_Intel
320 Views

Hello , I think i already replied to your message ..iam not sure why it is show up in the message window...

anyway ...It depends on the design ; Can you tell me how i can help u for the same ?

 

Thank you ,

 

Regards,

Sree

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RDiva
Novice
320 Views

I am not sure either. This was answered long back by someone else. I am good on it.

Divakar

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SreekumarR_G_Intel
320 Views

Ok thank you much

 

Regards,

Sree

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