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Altera_Forum
Honored Contributor I
1,915 Views

Zentel A3S56D40ETP-G5 DDR-Ram Timing Problems

Hi, 

 

we have a Cyclone III Starter Kit. The DDR-Ram Chip is an Zentel A3S56D40ETP-G5. Refering to the specs of the chip, the timings are correct. No Preset is available in Quartus 9.1 (fully licensed). 

The hardware design is loadable onto the FPGA, but the Nios-II IDE is not able to load a programm into memory. It claims that the memory is not working correctly and gives a CRC- error. 

Any help appreciated! 

 

Best regards, 

 

froeben
0 Kudos
7 Replies
Altera_Forum
Honored Contributor I
62 Views

The first thing to do would be to compile the memory test example. For that you'll need a big on-chip ram, put everything there, execute it and have it test the DDR ram. 

Is it one of your own designs or did you use an example given with the kit?
Altera_Forum
Honored Contributor I
62 Views

I'm not shure which memory example you mean! 

 

First of all: We have code that worked with a PSC DDR-Ram chip but the board broke down and so we had to buy a new one! This one has another DDR-Ram chip. The specs of the chips are exactly the same even so the timing. But it doesn't work! 

 

The second: There is no preset for the DDR-Ram Chip! And no example of the DDR-Ram Configuration available!
Altera_Forum
Honored Contributor I
62 Views

In the Nios IDE when you start a new project, you can select the "memtest" template. I haven't tried the new BSP tool, but I guess it's there too. 

 

I believe the cycloneIII_3c25_start_niosII_standard given with the kit is using the DDR. Is it working on your new board?
Altera_Forum
Honored Contributor I
62 Views

We are not able to use the memtest template since there is not enough on-chip memory available!  

The cycloneIII_3c25_start_niosII_standard which is given with the kit, using DDR is much to old!
Altera_Forum
Honored Contributor I
62 Views

Can't you recompile the project with all the optimisations and reduced C library? Maybe it would fit then. 

What do you mean by too old? If all the timing parameters are the same, it should work.
Altera_Forum
Honored Contributor I
62 Views

The fitting is not the problem! It fits and it is loadable onto the FPGA, but the DDR-Ram is not usable!

Altera_Forum
Honored Contributor I
62 Views

I have problems following you... you just said that you couldn't fit the memory test example in the on-chip RAM and I gave you ideas to make it fit.