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Altera_Forum
Honored Contributor I
994 Views

about Spansion flash

Hi, 

 

I use Spansion flash S29GL256N on Stratix II GX audio-video development board. I checked the datasheet and it should be OK to use the AMD29LV128M flash driver that is provied as Presets by altera. But it did not work directly. Is there something special that i should look into when using Spansion flash instead of AMD flash? I really appreciate the help if you have relevant experience about it.
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32 Replies
Altera_Forum
Honored Contributor I
70 Views

I never could get that flash to work either (not that I tried for long). The example projects that ship with the audio-video board have a test app that tests the flash. In that example, they used a custom driver for the flash which they failed to provide. Let me know when you get it working. 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

thanks for the reply! :) In the shipped project for flash test the component spansion_512_0 is missing and i can not create the right new component using the shipped spansion_512.v file. I have created a new "service request" to Altera and i will keep you posted when i get the response from them.  

 

By the way, may i ask have you tested the ethernet function on this board? Since i can not get the flash work at this moment i got some problem when trying to modify the simple socket server example to test the ethernet function.
Altera_Forum
Honored Contributor I
70 Views

Yes I have used the ethernet and it works without issue. Here is a modified "network_utilities.c" file that you can use in the Simple Socket Server example that just hard-codes the MAC address. You'll have to rename it from "network_utlities.c.txt". 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

Thank you so much for the quick reply! I will test it as soon as i get access to the board tomorrow morning and i really appreicate the help!
Altera_Forum
Honored Contributor I
70 Views

Hi, 

 

My ethernet function still does not work. I get the same kind of error "ERROR : MAC Group[0] - No PHY connected!". What have i done wrong? 

My top level file looks like: 

*************************************************** 

module ddr2_test_top( 

enet_rx_dv, 

enet_rx_crs, 

enet_rx_col, 

enet_rx_clk, 

enet_tx_clk, 

enet_rx_er, 

pb_user_resetn, 

clk, 

enet_rxd, 

enet_tx_en, 

enet_gtx_clk, 

enet_tx_er, 

mdc, 

ddr2_cas_n, 

ddr2_rasn, 

ddr2_wen, 

mdio, 

ddr2_a, 

ddr2_ba, 

ddr2_cke, 

ddr2_clk_n, 

ddr2_clk_p, 

ddr2_csn, 

ddr2_dm, 

ddr2_dq, 

ddr2_dqs_p, 

ddr2_odt, 

enet_txd 

); 

 

input enet_rx_dv; 

input enet_rx_crs; 

input enet_rx_col; 

input enet_rx_clk; 

input enet_tx_clk; 

input enet_rx_er; 

input pb_user_resetn; 

input clk; 

input [7:0] enet_rxd; 

output enet_tx_en; 

output enet_gtx_clk; 

output enet_tx_er; 

output mdc; 

output ddr2_cas_n; 

output ddr2_rasn; 

output ddr2_wen; 

inout mdio; 

output [13:0] ddr2_a; 

output [1:0] ddr2_ba; 

output [0:0] ddr2_cke; 

inout [2:0] ddr2_clk_n; 

inout [2:0] ddr2_clk_p; 

output [0:0] ddr2_csn; 

output [0:0] ddr2_dm; 

inout [7:0] ddr2_dq; 

inout [0:0] ddr2_dqs_p; 

output [0:0] ddr2_odt; 

output [7:0] enet_txd; 

 

wire SYNTHESIZED_WIRE_0; 

wire SYNTHESIZED_WIRE_1; 

wire SYNTHESIZED_WIRE_2; 

wire SYNTHESIZED_WIRE_3; 

wire SYNTHESIZED_WIRE_4; 

wire SYNTHESIZED_WIRE_5; 

wire SYNTHESIZED_WIRE_6; 

wire SYNTHESIZED_WIRE_24; 

wire SYNTHESIZED_WIRE_9; 

wire [7:0] SYNTHESIZED_WIRE_10; 

wire [3:0] SYNTHESIZED_WIRE_11; 

wire SYNTHESIZED_WIRE_25; 

wire SYNTHESIZED_WIRE_14; 

wire SYNTHESIZED_WIRE_15; 

wire SYNTHESIZED_WIRE_16; 

wire SYNTHESIZED_WIRE_17; 

wire SYNTHESIZED_WIRE_18; 

wire SYNTHESIZED_WIRE_19; 

wire SYNTHESIZED_WIRE_20; 

wire SYNTHESIZED_WIRE_21; 

wire [7:0] SYNTHESIZED_WIRE_22; 

wire [3:0] SYNTHESIZED_WIRE_23; 

 

assign SYNTHESIZED_WIRE_24 = 0; 

 

 

 

 

nios_ddr2 b2v_inst(.clk_to_tse_pll(clk), 

.clk(clk), 

.reset_n(pb_user_resetn), 

.global_reset_n_to_the_ddr_sdram_0(pb_user_resetn), 

.gm_rx_dv_to_the_tse_mac(SYNTHESIZED_WIRE_0), 

.gm_rx_err_to_the_tse_mac(SYNTHESIZED_WIRE_1), 

.m_rx_col_to_the_tse_mac(SYNTHESIZED_WIRE_2), 

.m_rx_crs_to_the_tse_mac(SYNTHESIZED_WIRE_3), 

.m_rx_en_to_the_tse_mac(SYNTHESIZED_WIRE_4), 

.m_rx_err_to_the_tse_mac(SYNTHESIZED_WIRE_5), 

.mdio_in_to_the_tse_mac(SYNTHESIZED_WIRE_6), 

.rx_clk_to_the_tse_mac(enet_rx_clk), 

.set_1000_to_the_tse_mac(SYNTHESIZED_WIRE_24), 

.set_10_to_the_tse_mac(SYNTHESIZED_WIRE_24), 

.tx_clk_to_the_tse_mac(SYNTHESIZED_WIRE_9), 

.mem_dqs_to_and_from_the_ddr_sdram_0(ddr2_dqs_p), 

.gm_rx_d_to_the_tse_mac(SYNTHESIZED_WIRE_10), 

.m_rx_d_to_the_tse_mac(SYNTHESIZED_WIRE_11), 

.mem_clk_n_to_and_from_the_ddr_sdram_0(ddr2_clk_n), 

.mem_clk_to_and_from_the_ddr_sdram_0(ddr2_clk_p), 

.mem_dq_to_and_from_the_ddr_sdram_0(ddr2_dq), 

.tse_pll_c0(SYNTHESIZED_WIRE_14), 

.mem_cas_n_from_the_ddr_sdram_0(ddr2_cas_n), 

.mem_cke_from_the_ddr_sdram_0(ddr2_cke), 

.mem_cs_n_from_the_ddr_sdram_0(ddr2_csn), 

.mem_dm_from_the_ddr_sdram_0(ddr2_dm), 

.mem_odt_from_the_ddr_sdram_0(ddr2_odt), 

.mem_ras_n_from_the_ddr_sdram_0(ddr2_rasn), 

.mem_we_n_from_the_ddr_sdram_0(ddr2_wen), 

.eth_mode_from_the_tse_mac(SYNTHESIZED_WIRE_21), 

.gm_tx_en_from_the_tse_mac(SYNTHESIZED_WIRE_19), 

.gm_tx_err_from_the_tse_mac(SYNTHESIZED_WIRE_20), 

.m_tx_en_from_the_tse_mac(SYNTHESIZED_WIRE_17), 

.m_tx_err_from_the_tse_mac(SYNTHESIZED_WIRE_18), 

.mdc_from_the_tse_mac(mdc), 

.mdio_oen_from_the_tse_mac(SYNTHESIZED_WIRE_16), 

.mdio_out_from_the_tse_mac(SYNTHESIZED_WIRE_15), 

.gm_tx_d_from_the_tse_mac(SYNTHESIZED_WIRE_22), 

.m_tx_d_from_the_tse_mac(SYNTHESIZED_WIRE_23), 

.mem_addr_from_the_ddr_sdram_0(ddr2_a), 

.mem_ba_from_the_ddr_sdram_0(ddr2_ba)); 

 

 

gmii_mii_mux b2v_inst1(.reset_rx_clk(SYNTHESIZED_WIRE_25), 

.rx_clk(enet_rx_clk), 

.phy_rx_col(enet_rx_col), 

.phy_rx_crs(enet_rx_crs), 

.phy_rx_dv(enet_rx_dv), 

.phy_rx_err(enet_rx_er), 

.reset_tx_clk(SYNTHESIZED_WIRE_25), 

.tx_clk_ref125(SYNTHESIZED_WIRE_14), 

.tx_clk(enet_tx_clk),.mdio_out(SYNTHESIZED_WIRE_15), 

.mdio_oen(SYNTHESIZED_WIRE_16), 

.m_tx_en(SYNTHESIZED_WIRE_17), 

.m_tx_err(SYNTHESIZED_WIRE_18), 

.gm_tx_en(SYNTHESIZED_WIRE_19), 

.gm_tx_err(SYNTHESIZED_WIRE_20), 

.eth_mode(SYNTHESIZED_WIRE_21), 

.mdio(mdio), 

.gm_tx_d(SYNTHESIZED_WIRE_22), 

.m_tx_d(SYNTHESIZED_WIRE_23), 

.phy_rx_d(enet_rxd), 

.tx_clk_mac(SYNTHESIZED_WIRE_9), 

.gtx_clk(enet_gtx_clk), 

.phy_tx_en(enet_tx_en), 

.phy_tx_err(enet_tx_er), 

.mdio_in(SYNTHESIZED_WIRE_6), 

.m_rx_col(SYNTHESIZED_WIRE_2), 

.m_rx_crs(SYNTHESIZED_WIRE_3), 

.m_rx_dv(SYNTHESIZED_WIRE_4), 

.m_rx_err(SYNTHESIZED_WIRE_5), 

.gm_rx_dv(SYNTHESIZED_WIRE_0), 

.gm_rx_err(SYNTHESIZED_WIRE_1), 

.gm_rx_d(SYNTHESIZED_WIRE_10), 

.m_rx_d(SYNTHESIZED_WIRE_11), 

.phy_tx_d(enet_txd)); 

 

assign SYNTHESIZED_WIRE_25 = ~pb_user_resetn; 

 

endmodule 

 

**********************************************************
Altera_Forum
Honored Contributor I
70 Views

If the driver can't detect a PHY it's because it's unable to communicate with the PHY over the MDIO interface. This is basically an I2C interface involving the "mdc" and "mdio" pins. I'm not familiar with this gmii_mii_mux module that appears to interact with these signals somehow. 

 

Typically you make a simple assignment at the top level like this: 

 

module ddr2_test_top( ... mdc, mdio, ... ); wire mdio_out; wire mdio_oe; assign mdio = mdio_oen ? 1'bz : mdio_out; nios_ddr2 b2v_inst( ... .mdio_in_to_the_tse_mac(mdio), .mdio_out_from_the_tse_mac(mdio_out), .mdio_oen_from_the_tse_mac(mdio_oen), ... );
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

simply for test i used the TSE MAC in 10/100 Mhz small MAC mode. I removed the gmii_mii_mux module and modified my top level file. But still I got the error message that "ERROR : MAC Group[0] - No PHY connected!". I am really confused. Any response is appreciated. My top level file is: 

------------------------------------------------------------------- 

module ddr2_test_top( 

enet_rx_dv, 

enet_rx_crs, 

enet_rx_col, 

enet_rx_clk, 

enet_tx_clk, 

enet_rx_er, 

pb_user_resetn, 

clk, 

enet_rxd, 

enet_tx_en, 

 

enet_tx_er, 

mdc, 

ddr2_cas_n, 

ddr2_rasn, 

ddr2_wen, 

mdio, 

ddr2_a, 

ddr2_ba, 

ddr2_cke, 

ddr2_clk_n, 

ddr2_clk_p, 

ddr2_csn, 

ddr2_dm, 

ddr2_dq, 

ddr2_dqs_p, 

ddr2_odt, 

enet_txd 

); 

input enet_rx_dv; 

input enet_rx_crs; 

input enet_rx_col; 

input enet_rx_clk; 

input enet_tx_clk; 

input enet_rx_er; 

input pb_user_resetn; 

input clk; 

input [3:0] enet_rxd; 

output enet_tx_en; 

 

output enet_tx_er; 

output mdc; 

output ddr2_cas_n; 

output ddr2_rasn; 

output ddr2_wen; 

inout mdio; 

output [13:0] ddr2_a; 

output [1:0] ddr2_ba; 

output [0:0] ddr2_cke; 

inout [2:0] ddr2_clk_n; 

inout [2:0] ddr2_clk_p; 

output [0:0] ddr2_csn; 

output [0:0] ddr2_dm; 

inout [7:0] ddr2_dq; 

inout [0:0] ddr2_dqs_p; 

output [0:0] ddr2_odt; 

output [3:0] enet_txd; 

 

wire mdio_out; 

wire mdio_oen; 

 

 

assign wire_GND = 0; 

 

assign mdio = mdio_oen ? 1'bz : mdio_out; 

 

nios_ddr2 b2v_inst(.clk_to_tse_pll(clk), 

.clk(clk), 

.reset_n(pb_user_resetn), 

.global_reset_n_to_the_ddr_sdram_0(pb_user_resetn), 

.m_rx_col_to_the_tse_mac(enet_rx_col), 

.m_rx_crs_to_the_tse_mac(enet_rx_crs), 

.m_rx_d_to_the_tse_mac(enet_rxd), 

.m_rx_en_to_the_tse_mac(enet_rx_dv), 

.m_rx_err_to_the_tse_mac(enet_rx_er), 

.mdio_in_to_the_tse_mac(mdio), 

.rx_clk_to_the_tse_mac(enet_rx_clk), 

.tx_clk_to_the_tse_mac(enet_tx_clk), 

.mem_dqs_to_and_from_the_ddr_sdram_0(ddr2_dqs_p), 

.mem_clk_n_to_and_from_the_ddr_sdram_0(ddr2_clk_n), 

.mem_clk_to_and_from_the_ddr_sdram_0(ddr2_clk_p), 

.mem_dq_to_and_from_the_ddr_sdram_0(ddr2_dq), 

.mem_cas_n_from_the_ddr_sdram_0(ddr2_cas_n), 

.mem_cke_from_the_ddr_sdram_0(ddr2_cke), 

.mem_cs_n_from_the_ddr_sdram_0(ddr2_csn), 

.mem_dm_from_the_ddr_sdram_0(ddr2_dm), 

.mem_odt_from_the_ddr_sdram_0(ddr2_odt), 

.mem_ras_n_from_the_ddr_sdram_0(ddr2_rasn), 

.mem_we_n_from_the_ddr_sdram_0(ddr2_wen), 

.eth_mode_from_the_tse_mac(wire_GND), 

.m_tx_en_from_the_tse_mac(enet_tx_en), 

.m_tx_err_from_the_tse_mac(enet_tx_er), 

.mdc_from_the_tse_mac(mdc), 

.mdio_oen_from_the_tse_mac(mdio_oen), 

.mdio_out_from_the_tse_mac(mdio_out), 

.m_tx_d_from_the_tse_mac(enet_txd), 

.mem_addr_from_the_ddr_sdram_0(ddr2_a), 

.mem_ba_from_the_ddr_sdram_0(ddr2_ba)); 

 

 

endmodule 

------------------------------------------------------------ 

Altera_Forum
Honored Contributor I
70 Views

yeah that's strange ... 

 

1 - Are your pin assignments all correct? These are what I show: 

set_location_assignment PIN_D13 -to enet_mdc 

set_location_assignment PIN_C13 -to enet_mdio 

It looks like you changed the names, did you also add pin assignments for the new names? 

 

2 - Can you scope the mdc and mdio pins at the PHY to see if they are toggling? 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

I have not changed the name of pins and i have checked the pin assignment again. The PHY on this board is very difficult to measure mdc or mdio signals. Do you have some suggestions that i can verify the interface for the PHY?
Altera_Forum
Honored Contributor I
70 Views

Hi. 

You don't have any original example for that board, to check if it is working well ??
Altera_Forum
Honored Contributor I
70 Views

I can probably work you up a simple example design that you can just run but you'll have to bare with me as I can only work it in between other things. If I can't get it to you today then perhaps tomorrow. 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi, 

 

the shipped ethernet interface test project enet_loopback did not work on my board. When i oppened the sopc system using quartus 8.0 sp1 it was reported that the component md_cfg_interface_v3_0 is missing. I have created service request to altera and have not got any response yet. That's why i turned to the simple socket server exampe for ethernet interface test. 

 

and to Jake, i would really appreciate it if you could send me some test program.
Altera_Forum
Honored Contributor I
70 Views

Okay give this is a shot. It runs on my board. This example uses the Avalon OpenCores 10/100 Ethernet MAC rather than the Altera TSE MAC.  

 

I've included the SOF file in the ZIP file so you can just program it but you'll want to recompile the project to see how it's structured. I couldn't include the database files for size. 

In order to recompile you'll also need the Avalon OpenCores MAC which is available here: 

http://www.alteraforum.com/forum/showthread.php?t=3665 

You'll need to unzip this in the c:\altera\80\ip\sopc_builder_ip\ folder. 

 

As far as the software goes. I've hard-coded the MAC address and set the static IP address to 192.168.1.50. 

 

So to run it, you'll need to program the SOF into the board, then use the IDE to download and run the simple-socket server example. This example is running out of the SSRAM on the board. 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

Thank you so much for the example! I have tested it on my board and it works fine! So now i can compare your design example with mine and try to understand what i have done wrong. I have not re-compiled your design yet so i may bother you in the future ... Many thanks.
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

Do you know how to tune the ethernet opencore parameters to remove the timing issue? Now i have the timing warnings concerning eth_rx_clk. Thank you in advance.
Altera_Forum
Honored Contributor I
70 Views

You'll need to be more specific. What paths are failing timing on the RX path? 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

 

This is what i got in messages. 

Critical Warning: Timing requirements not met 

Info: Worst-case hold slack is -0.588 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: -0.588 -0.588 eth_rx_clk  

Info: 0.041 0.000 eth_tx_clk  

Info: 0.341 0.000 clk_fpga  

Info: 0.341 0.000 clk_sopc  

Info: 0.341 0.000 io_clk  

Info: 5.421 0.000 ssram_clk_int  

Info: 9.500 0.000 n/a  

 

and i use your .sdc file for the timing setting.
Altera_Forum
Honored Contributor I
70 Views

Can you send me your archived project? In the meantime, I would assume you can ignore the issue. 

 

Jake
Altera_Forum
Honored Contributor I
70 Views

Hi Jake, 

If you get the time check the archived project which is pretty much the same as your reference design. Although there is timing warning the design works. But it seems that the eth_rx_clk, eth_tx_clk should be fine tuned concerning timing constraints if i want to use the opencore and add some other big logic blocks.