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altera modelsim, I am using a Cyclon v with quartus 13.1. under windows 10. In the simulation pll clock output, lock are undefined status after reset. maurizio stefani

mstef1
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Rahul_S_Intel1
Employee
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Hi ,

I tried on 13.1 the PLL simulation is working, can you please try to make a standalone pll and try the simulation.

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