altera_reserved_tck hold timing violation

[AEsqu]

In the help document:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10082012_359.html

it is mentioned to set altera_reserved_tck on global signal to avoid hold time violation,

but doing this give this error on quartus 19.3 arria 10:

Error: Peak virtual memory: 3362 megabytes 

Error: Processing ended: Wed Jan 15 16:59:29 2020 

Error: Elapsed time: 00:01:04 

Error: System process ID: 55512 

Error(13181): Source of port TCK in JTAG block auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom must be pin 

Error(16297): An error has occurred while trying to initialize the plan stage. 

Error: Quartus Prime Fitter was unsuccessful. 2 errors, 46 warnings 

Error: Peak virtual memory: 3362 megabytes 

Error: Processing ended: Wed Jan 15 16:59:29 2020 

Error: Elapsed time: 00:01:04 

Error: System process ID: 55512 

Error(293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 1146 warnings 

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to altera_reserved_tck -entity Achilles_arria_X

[KhaiChein_Y_Intel]

Hi,

This error is not related to the Global Clock assignment. The error indicates that the source that feeds the specified port in the specified JTAG block is not a pin. You have to modify the design so that the source of the port is a pin.

Thanks.

[AEsqu]

Hi YY,

This error only occurs when I add the QSF line for global clock:

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to altera_reserved_tck -entity Achilles_arria_X

Nothing else has changed in RTL.

Removing the line solves the issue.

[KhaiChein_Y_Intel]

Hi,

Could you provide a small test case for investigation?

Thanks.

[AEsqu]

Could you take one of your arria 10 test case and add that line in the qsf?

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to altera_reserved_tck 

[KhaiChein_Y_Intel]

Hi,

Every design has its own assignments/settings that contribute to different compilation result. It would be great if you could provide the design. It doesnt need to be the full design, a simple testcase would be helpful.

Thanks.

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates?

Thanks.

[AEsqu]

Hi, Quartus 19.4 has solved the issue, I do not need to assign any altera_* constraints anymore.

Ticket can be closed.

[KhaiChein_Y_Intel]

Hi,

Thanks for the update. I believe it is useful for other users.

Thanks.

Best regards,

Khai Y