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arria 10 DDR3 fitter DM&DQ fault


 Unable to place DM pin adjacent to a DQ pin. Constrain the DM pin and a DQ pin to I/O locations that form a differential pair

I plant the DM pin and DQ pin both in same bank.

QSF file:

set_location_assignment PIN_J27 -to emif_0_mem_mem_cke[0]

set_location_assignment PIN_K24 -to emif_0_mem_mem_cs_n[0]

set_location_assignment PIN_B26 -to emif_0_mem_mem_dm[0]

set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to emif_0_mem_mem_cke[0]

set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to emif_0_mem_mem_cs_n[0]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dm[0]

set_location_assignment PIN_K25 -to emif_0_mem_mem_odt[0]

set_location_assignment PIN_F23 -to emif_0_mem_mem_ras_n[0]

set_location_assignment PIN_L24 -to emif_0_mem_mem_reset_n[0]

set_location_assignment PIN_M24 -to emif_0_mem_mem_we_n[0]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[0]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[1]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[2]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[3]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[4]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[5]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[6]

set_instance_assignment -name IO_STANDARD "SSTL-15" -to emif_0_mem_mem_dq[7]

set_location_assignment PIN_C23 -to emif_0_mem_mem_dq[0]

set_location_assignment PIN_B23 -to emif_0_mem_mem_dq[1]

set_location_assignment PIN_B27 -to emif_0_mem_mem_dq[2]

set_location_assignment PIN_C27 -to emif_0_mem_mem_dq[3]

set_location_assignment PIN_A25 -to emif_0_mem_mem_dq[4]

set_location_assignment PIN_B25 -to emif_0_mem_mem_dq[5]

set_location_assignment PIN_A24 -to emif_0_mem_mem_dq[6]

set_location_assignment PIN_A23 -to emif_0_mem_mem_dq[7]


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Honored Contributor III

The easiest way to make sure you have valid placement is to enable the DDR memory view in the Pin Planner. In the View menu, select the view for the size of your DQS groups (x8) and the Pin Planner will indicate which pins you can/should use for DQ, DQS, and DM.


If you want a more thorough analysis, you can use the Interface Planner tool to select a valid legal location for the entire interface and have it validated on the fly.



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