FPGA, SoC, And CPLD Boards And Kits

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

FPGA, SoC, And CPLD Boards And Kits

Discussions

Problem in configuring Cyclone V GT development kit pins for 1.2V voltage level

Bus error on memory operation

Ds-5 debug on Arria 10 Reflex Alaric board.

Arria 10 SoC DevKit - IP for building GSRD hardware design

quartus with arria10 dev board supports all arria10 devices?

de10-nano. Barrel connector specs

Just got development board, need help installing..

DE10-NANO - NIOS+ADC+DMA+ONCHIP MEMORY+HDMI on Platform Designer

Alternate programs to use the HPS in DE1-SoC?

DE10-Nano CDC Serial...

SDRAM rzqin pin on Arria V starter kit

MegaCore Function Generation Error. IP Functional Simulation Model Creation Failed.

Altera monitor program.

de10_nano to drive cam

DE0 NANO SoC rev.B Can't access JTAG chain

Featured Content

Ethernet access via FPGA in DE10 nano board

Nios to FPGA Avalon-MM

Request for Stratix 10 AX FPGA Development Kit User Guide and Documentation Links

Re: Ethernet access via FPGA in DE10 nano board

Re: clocking GPIO

Re: DE1-SoC board outline?