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Altera_Forum
Honored Contributor I
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board test system compile error even after patch (cyclone IV GX starter kit)

Hi - I just began working with a Cyclone IV GX Starter Kit and attempted to compile the board test system (bts_general), but got the error: 

 

Error: Port INCLK of Transceiver PLL Atom bts_general_sopc:bts_general_sopc_inst|tse_mac:the_tse_mac|altera_tse_mac_pcs_pma_gige:altera_tse_mac_pcs_pma_gige_inst|altera_tse_gxb_gige_inst:the_altera_tse_gxb_gige_inst|altera_tse_altgx_civgx_gige_wo_rmfifo:the_altera_tse_alt_gx_civgx_wo_rmfifo|altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_mlv7:altera_tse_altgx_civgx_gige_wo_rmfifo_alt_c3gxb_mlv7_component|altpll:pll0|altpll_ja81:auto_generated|pll1 cannot be connected to PLL Atom pll_125:this_pll_125|altpll:altpll_component|pll_125_altpll:auto_generated|pll1 

 

After googling, the only relevant result seemed to be: 

http://www.altera.com/support/kdb/solutions/rd12132010_299.html 

 

I installed the windows version patch and verified that it seemed to be patching the correct files (c:\altera\10.1\quartus\bin\db_cut.dll), but despite applying the patch I still get the same compilation error. 

 

Is there some reason the patch did not correct the problem (are there any specific temp files I need to blow away?)? Anyone successfully compiled / programmed the board_test_system for this kit in quartus 10.1? 

 

Thanks in advance.
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Altera_Forum
Honored Contributor I
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Try bypassing the pll instantiated at the top level. Hook the 125 MHz clock input directly to the sopc system. 

 

bts_general_sopc bts_general_sopc_inst 

.chipselect_to_the_tristate_lcd (lcd_csn), 

.flash_tristate_bridge_address (fsml_a), 

.flash_tristate_bridge_data (fsml_d), 

.flash_tristate_bridge_readn (fsml_oen), 

.flash_tristate_bridge_writen (fsml_wen), 

.select_n_to_the_ext_flash (flash_cen), 

.cs_n_to_the_maxII_interface (max2_csn), 

.ssram_bwn_to_the_ssram (ssram_bwn), 

.ssram_cen_to_the_ssram (ssram_cen),  

.in_port_to_the_button_pio (user_pb), 

.out_port_from_the_led_pio (user_led), 

.mdc_from_the_tse_mac (enet_mdc), 

.mdio_in_to_the_tse_mac (mdio_in_to_the_tse_mac), 

.mdio_oen_from_the_tse_mac (mdio_oen_from_the_tse_mac), 

.mdio_out_from_the_tse_mac (mdio_out_from_the_tse_mac), 

.led_an_from_the_tse_mac (led_an_from_the_tse_mac), 

.led_char_err_from_the_tse_mac (led_char_err_from_the_tse_mac), 

.led_col_from_the_tse_mac (led_col_from_the_tse_mac), 

.led_crs_from_the_tse_mac (led_crs_from_the_tse_mac), 

.led_disp_err_from_the_tse_mac (led_disp_err_from_the_tse_mac), 

.led_link_from_the_tse_mac (led_link_from_the_tse_mac), 

// .gxb_cal_blk_clk_to_the_tse_mac (pll_clkin_enet), <---- Here ... 

.gxb_cal_blk_clk_to_the_tse_mac (clkin_enet),  

.reconfig_clk_to_the_tse_mac (clkin_sys), 

.reconfig_fromgxb_from_the_tse_mac (reconfig_fromgxb_from_the_tse_mac), 

.reconfig_togxb_to_the_tse_mac (reconfig_togxb_to_the_tse_mac), 

// .ref_clk_to_the_tse_mac (pll_clkin_enet), <---- ... and here 

.ref_clk_to_the_tse_mac (clkin_enet),  

.txp_from_the_tse_mac (enet_tx), 

.rxp_to_the_tse_mac (enet_rx), 

.osc_clk (clkin_sys), 

.ssram_clk (ssram_clk), 

.reset_n (cpu_resetn) 

);
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