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can MAX10 FPGA part “10M50DAF672I7G" support LVCMOS 1V standard

vlata
Employee
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We have used MAX10 FPGA part “10M50DAF672I7G"  for one board and we need to connect the FPGA GPIO with LVCMOS 1V interface. As per datasheet it is mentioned that this series will support the LVCMOS 1V rather than Bank 1B and Bank8. That why we have used bank4 to bank7 for LVCMOS 1V GPIO. 

So We tried to configure IO voltage to 1.0V, Quartus tool throwed error saying that not supported 1.0V. But Data sheet says it is supported. Can anybody help on resolving this query?

This is critical for us. I have attached error snapshot and datasheet snapshots.

Please help to resolve this query.

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AqidAyman_Intel
Employee
626 Views

May I know which version of Quartus Prime are you use?


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vlata
Employee
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Thank you for supporting We are using 20.1.1. Is it due to version?

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FvM
Valued Contributor III
609 Views
Hi,
you may have noticed that the same question was asked shortly before.
The answer is in the other thread, yes it's a version problem.
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vlata
Employee
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We have run in Quartus 22.1 version now error is not showing for  BANK 4 to BANK 7 regarding LVCMOS 1v gpio but some critical warnings are showing  on total mutual inductance. Please refer to the critical warning message below.

 

Critical Warning (21688): The total mutual inductance (Lm) of 1.0 V I/O pin R24 with surrounding 1.0 V I/O pins is 7.446000 nH. This is not allowed. The total mutual inductance must be less than or equal to 7.41 nH

 

Can you please help us why these warning is showing , these banks will support LVCMOS 1v or Not?

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AqidAyman_Intel
Employee
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Hi,


You need to refer to this User Guide from the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683751/22-1/guidelines-placement-restrictions-for.html


You need to ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines.


Regards,

Aqid


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