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Altera_Forum
Honored Contributor I
952 Views

communication between Cyclone III and MAX II in Cyclone III development kit

Hello, 

 

We are working on Cyclone III 120 dev. kit. I could not figure it out from the reference manual about communication facility between MAXII and Cyclone III devices.  

 

my task is to implement USB interface device in MAXII device and access that from FPGA. Unfortunately I could not find the pins between MAX II and Cyclone III for this purpose. 

 

Any Suggestions please. 

 

Thanks 

Trinath
0 Kudos
12 Replies
Altera_Forum
Honored Contributor I
95 Views

 

--- Quote Start ---  

my task is to implement USB interface device in MAXII device 

--- Quote End ---  

 

You can't put new logic into the MAX II device without loosing the embedded USB Blaster functionality. 

 

 

--- Quote Start ---  

I could not figure it out from the reference manual about communication facility between MAXII and Cyclone III devices. 

--- Quote End ---  

 

I see, that there's a complete USB_PHY_xxx bus provided in the hardware design. But I didn't yet see any related Dev Kit documentation. My assumption is, that Altera planned to include a defined interface to USB PHY in the MAX II logic, but either didn't yet implement it or omit it from the documentation. You may want to ask Altera support about the intended use of USB_PHY_xxx signals respectively a suggested way to utilize the USB interface for user communication. 

 

Previous Dev Kits usually had a second USB interface for user communication. Most likely it has been regarded by Altera as waste of resources, because it was used very rarely. The USB_PHY_xxx interface seems to be a successor, apparently still under construction.
Altera_Forum
Honored Contributor I
95 Views

Thanks for the suggestions FvM. I will ask Altera about USB_PHY_xxx usage. 

 

I have a question here. So, If I erase the MAXII logic and implement a USB interface inside it, do you think it is possible to use those JTAG Config and PM config lines (as shown in fig 2-3, page 2-7 in Cyclone III reference manual) to send USB_FIFO status lines like full, empty, data present ... 

 

Thanks again
Altera_Forum
Honored Contributor I
95 Views

The usb data bus is providing signals for this purpose.

Altera_Forum
Honored Contributor I
95 Views

I checked the schematic between MAX II and FPGA. The USB Data Bus as shown in fig 2-3 indicates 8 data lines only. not the control signals.

Altera_Forum
Honored Contributor I
95 Views

You are right. I didn't see the Cypress USB 2.0 controller and thought, USB_PHY_xxx are also connected to the FPGA. But they aren't. This mainly emphasizes the question, how the USB operation is intended in the design. Sorry for causing confusion. But the CIII 120 Dev Kit seems to be somewhat mysterious.  

 

I think now, that USB_PHY access is planned through MAX II and the shared bus. But I don't know, if there's is already respective logic included in the factory default MAX II design. Please consider, that I don't have the Dev Kit and possibly missed some documentation or example software updates, that may clarify the said questions.
Altera_Forum
Honored Contributor I
95 Views

I have the kit and can't give more information either. The least you can say about Altera's CIII development kit is that it's lacking documentation and design examples. Even a simple Ethernet design is a pain to set up...

Altera_Forum
Honored Contributor I
95 Views

@FvM, 

 

I contacted Altera support about this issue. And, here is what I got 

 

--- Quote Start ---  

 

Cypress USB device Cy7C68013A is an USB 2.0 High speed device. 

 

To enable the highest-speed PHY (Cypress) you will need to remove the suppression chip SN65220 and two 27-ohm isolation resistors between the USB connector and FTDI PHY. The MAXII needs to be re-programmed to hold the FTDI in reset and de-assert the Cypress device reset. 

 

Once the MAXII has been re-programmed the embedded blaster, power monitor, and JTAG bus switch will no longer function. Use an external blaster and re-direct JTAG between the MAXII-only and the FPGA-only through the DEV_SEL jumper. 

 

FTDI device is used by on-board USB Blaster. The customer can’t use this device. Cypress USB device Cy7C68013A is a USB interface device with an 8051 MCU in it. You can program the embedded 8051 MCU to transfer data between the Cy7C68013 and the PC. You can contact Cypress (http://www.cypress.com (http://www.cypress.com/)) if you need more information about it. 

 

There is not any reference design or example design covered th " 

 

--- Quote End ---  

 

Now the question again is, How do I communicate with Cypress from Cyclone?:confused:
Altera_Forum
Honored Contributor I
95 Views

The support response clarifies, that user USB communication must be regarded as an unsupported feature with the CIII 12ß Dev Kit. A hardware options is provided, but nothing more. 

 

As a first comment, I don't understand this support statement: 

 

--- Quote Start ---  

FTDI device is used by on-board USB Blaster. The customer can’t use this device. 

--- Quote End ---  

In my opinion, you can use the FTDI device for user communication with reprogrammed MAX II. I would always prefer it for low and medium throughput, because of an easy programming interface. 

 

If you don't mind, that the FTDI device enumerates as USB Blaster, you can keep the EEPROM settings and access the device through FTDI DLLs anyway, otherwise you can reprogram the EEPROM with the FTDI Mprog tool. 

 

As I mentioned previously, the shared bus is an option to connect the USB_PHY (through MAX II) to the FPGA. Also USB_PHY_FD[7..0] provide an 8-bit data connection to both USB devices. But to utilize the Cypress device at USB high speed, a 16 bit data interface is required, I think.
Altera_Forum
Honored Contributor I
95 Views

Even though I reprogram MAXII, following is the pin configuration between MAXII and CycloneIII 

8 Bidirectional pins, 

4 output from MAXII and Input to CycloneIII (Jtag pins) 

 

to access the FTDI, I need to assert WR# and RD# signals from FPGA where my logic resides. And, I doubt any provision for that. 

 

I am thinking of to return the dev. kit to Altera, and probably go with my current CycloneII kit and get a um245r dip module (http://www.ftdichip.com/products/evaluationkits/um245r.htm) from FTDI.
Altera_Forum
Honored Contributor I
95 Views

You should check the Dev Kit circuit diagrams more thoroughly. I see not less than 13 signals connecting MAX II and FPGA, that can be freely assigned, if you replace the MAX II configuration: 

USB_FD[7..0] 

USB_FULL 

USB_EMPTY 

USB_REN 

USB_WEN 

USB_CMD_DATA 

 

Also these signals are optionally free for your assignment 

MAX_OEN 

MAX_WEN 

MAX_CSN 

 

It should be checked however, if these signals are possibly wired in the MAXII default configuration, although Altera support doesn't know about.
Altera_Forum
Honored Contributor I
95 Views

hmmm, I did not see those lines until yesterday. Thanks for giving the info. I am trying use those lines. no luck till now.

Altera_Forum
Honored Contributor I
95 Views

As said before, the definition of USB data and control signal seems to indicate that an interface concept was guiding the Dev Kit designers. It's still a pending question, if respective logic has been already implemented in the MAX II factory design or if it's just a feature to come.

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