convert avalon bus to AXI4-Lite

[ZhiqiangLiang]

Hi,

My FPGA model is:

Cyclone 10 LP 10CL120.

I am now using Quartus II 18.1.

In FPGA, I added NIOS II, and  I would like to convert avalon bus to AXI4 LIte master. It means that NIOS will send out avalon signal, and the receiver is AXI4 Lite master.

the questions are:

1) is there any in chip IP adapter that can convert avalon to axi4 lite master?

2) if there is no IP adapter in chip, is there any sample code or reference?

[sstrell]

An AXI4-Lite manager (they don't call it master any more) would not be able to receive commands.  That would be an AXI4-Lite subordinate that receives and processes commands.  You can connect the Avalon host (previously referred to as master) interfaces to AX4-Lite subordinate interfaces directly in Platform Designer.  No adaptor is needed since the interconnect will get built automatically to support this.

And if possible, if this is a new design, you should use a newer version of Quartus and use a Nios V processor instead.

[ZhiqiangLiang]

Thank you @sstrell 

Is there any tutorial or example about how to operate Platform Designer to connect AXI4 Lite subordinate?

It took me a few day in the past to try how to user Platform Designer.   but I still don't know how to use it.

[sstrell]

You simply make standard connections in the tool between the interfaces of the components that need to be connected.  The user guide is here: https://www.intel.com/content/www/us/en/docs/programmable/683364.html

There's training here: https://learning.intel.com/Developer/learn/courses/389/creating-a-system-design-with-platform-designer-getting-started

[ZhiqiangLiang]

Thank you @sstrell 

I am now creating a new NIOS II project.

If I add EPCS to the project, I experience the issue "EPCS is not supproted in Cyclone 10 LP family".

The question is:

if I don't add EPCS, what should be added to burn firmware?

[sstrell]

Your configuration options are here: https://www.intel.com/content/www/us/en/docs/programmable/683879/current/configuration.html

[RichardTanSY_Altera]

Thank you Sstrell for the answers.

@ZhiqiangLiang, do you have further inquiry?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Altera 

Thank you!

I have many questions to use Cyclone 10 LP 10CL120.

My company buy the FPGA, and produce the PCB board. however, we can't power on it.

For example, my questions are:

1) whether we should connect a crystal oscilator to which pin of FPGA.

2) how to use Quartus to constrain signal node to GPIO pins.

3) I would like to run NIOS II in FPGA, however I don't know how to enable burning firmware interface.

4) and etc.

Our product previously used ZYNQ7000 of Xilinx, but Now, we are going to use Cyclone10LP.

Would you please contact me by my email: dpstill@126.com.

By the way, I previously worked in Intel as well.

[RichardTanSY_Altera]

1) You can assign it to the Dedicated Clock pin. You can check this in the Pin Planner > Task window> Highlight Pins > Clock Pins

2) Same with (1) You can assign pins using Pin Planner. Go to Assignments > Pin Planner.

Find your signal (e.g. led[0]) and assign it to a physical pin (e.g. PIN_AJ5).

Alternatively, you can manually constraints via .qsf constraints file:

 set_location_assignment PIN_AJ5 -to led[0]

https://www.intel.com/content/www/us/en/docs/programmable/683492/18-1/assigning-i-o-pins.html

Additionally, you can refer to the user guide below to check the legality of pin assignments, using I/O Assignment Analysis:

https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/guideline-use-i-o-assignment-analysis.html

3) As this question is related to configuration area, unfortunately, I am not expert in that particular area . Could you help to create a new forum case so an agent will be assigned to your case. Thank you for your understanding. 

Regards,

Richard Tan

[ZhiqiangLiang]

Thank you @RichardTanSY_Altera 

I have tried Pin Planner. The problems about Pin Planner are:

1) I don't know how to assign clk to which FPGA pin.

2) For example, the input crystal oscillator is  26MHz, but FPGA internal needs 160MHz. how to set FPGA PLL?

3) in Pin Planner, I can set some general GPIO, but the exported file is TCL which is not sdc file. should I convert the TCL file to sdc file? what is the difference? 

4) If I would like to manually write sdc file, what is format of sdc file? how to write the beginning of the sdc file?

5) once I finish the sdc file or Pin Planner, how to use it in Quartus?

[sstrell]

1) You can drag and drop signals to make pin assignments in the Pin Planner.  Dedicated clock input pins are indicated with a little waveform symbol on them.

2) The PLL is an IP you can parameterize so you can set what the output frequency should be based on the input frequency.

3) There's no need to export any files from the Pin Planner.  The assignments are placed in the .qsf file as Richard mentioned.  And a .sdc file is for timing constraints.  It has nothing to do with pin assignments other than using the names of the top-level I/O signals for creating I/O timing constraints.

4) Again, not clear if you are still talking about pin assignments or if you need help with timing constraints.  Check the Timing Analyzer user guide for the latter: https://www.intel.com/content/www/us/en/docs/programmable/683068.html

5) .sdc file is added to the Timing Analyzer settings in the Settings dialog box from the Assignments menu.  And as mentioned, pin assignments are automatically added to the .qsf file as you make them in the Pin Planner.

[RichardTanSY_Altera]

Do you need further help in regards to this case?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Altera 

Thank you!
Currently, no more questions as we are now debugging Cyclone10 on PCB.

Once the debugging is done, I may have further questions about avalon and axi4 lite

[RichardTanSY_Altera]

Glad to hear that. Thanks to @sstrell for helping to answer the latter part.

May I know if the debug process will take some time?

If it’s expected to take a while, I suggest we close this thread for now and open a new case to continue the discussion.

Does that sound good to you?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Altera 

The debugging will take place in 3 days.

[RichardTanSY_Altera]

Any update on this?

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

Please kindly create a new forum post for your further inquiries about avalon and axi4 lite.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan

[ZhiqiangLiang]

@sstrell 

@RichardTanSY_Altera 

Thank you for your reply!

In the past a few days, I have been debugging the system in Cyclone 10.

I did the following things:

1) In Platform Designer, I create a new IP whose name BF5V. Please see the following picture.

2) the interface of my IP is AXI4Lite.

3) I convert Avalon to AXI4Lite. please see the picture below.

4)  in C code,  I try to control ADC and etc, and I can control them successfully. however, If I use the following C code to write Avalon bus,  the data in S_AXI_AWDATA is not as expected. For example, I write 0x55AA, 0x33, 0x0001, 0x4000 to the bus, but the data on S_AXI_AWDATA is 0x55AA, 0x33, 0x4000. The data 0x0001 is missing.

Is there any doc about how to convert Avalon to AXI4Lite?

[RichardTanSY_Altera]

I am not familiar with C code and Nios II. Could you file a new forum case for your follow up question? 

Perhaps you can try to attend the instructor-led training class which occur live on 29th/39th May depending on your region, they provide hands-on training on creating PD system. Hopefully it will helps you to further understand. 
https://learning.intel.com/Developer/learn/courses/982/introduction-to-platform-designer-building-systems

FYI, you can check your calendar for upcoming classes.

Regards,
Richard Tan

[sstrell]

Your first screenshot is blocking signal names in Signal Tap and your third screenshot is blocking the addresses that are to be accessed in the new component (guessing it's 0x80000 from the code), so it's difficult to correlate what you are showing in hardware with the code.  What address are these data values being written to?  That doesn't appear in the code either.

Is FPGA_SCAN_WRITE supposed to be the write enable signal so why would it appear on the data bus?

If you're coding Avalon, address and data should be put on the bus simultaneously on the separate signals (address and writedata).  These would then translate on the separate channels on the AXI side on different signals: write address channel (AWADDR), write channel (WDATA), write response channel (BRESP).

Is your design meeting timing?

More explanation of your code and seeing actual hardware addresses and setup would help.

Link to the Avalon spec as well: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interfaces.html

[ZhiqiangLiang]

@sstrell 

Please refer to my pseudo-code as follows.

I am 100% sure the test C code, verilog code, and everything things are correct.

The axi4lite Verilog code in my project has previously used and verified in my old project, so I confirm Verilog code of Axi4Lite is correct.

My main uncertainty, doubts and concerns are:

1) whether I connect/configured avalon to axi4lite correctly.

2) I left shift 2bits of the bias address of those registers in C code. I don't know whether is correct or not.

Please help to confirm my upper doubts based on the pictures and pseudo-code I pasted.

In Verilog code, I defined registers:
`define SCAN_WADDR_N 6'h18 // 60 <-- 0x18 Left shift 2 bits
`define SCAN_WDATA_N 6'h19 // 64
`define SCAN_WRITE_N 6'h1A // 68

In C code, I access those registers by the following address:
#define FPGA_SCAN_WADDR (FPGA_REGS_ADDR + (0x18<<2))
#define FPGA_SCAN_WDATA (FPGA_REGS_ADDR + (0x19<<2))
#define FPGA_SCAN_WRITE (FPGA_REGS_ADDR + (0x1A<<2))

In system.h in BSP:
#define ALT_MODULE_CLASS_BF5V_0 BF5V
#define BF5V_0_BASE 0x80000 // this address is the same as that in Platform Designer
#define BF5V_0_IRQ -1
#define BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BF5V_0_NAME "/dev/BF5V_0"
#define BF5V_0_SPAN 256
#define BF5V_0_TYPE "BF5V"

The test C code is:
int main()
{

while(1)
{
FPGA_Write(FPGA_SCAN_WADDR, 0x55AA); // write address
FPGA_Write(FPGA_SCAN_WDATA, 0x33); // write data
FPGA_Write(FPGA_SCAN_WRITE, 0x0001); // write enable signal
FPGA_Write(FPGA_SCAN_WRITE, 0x0000); // clear write enable signal
}
return 1;
}