csv pin assignement file for NIOS II Stratix II EP2S60F672C5ES Development Kit

[Altera_Forum]

I have a Nios II Development Kit Stratix ii Edition with the EP2S60F672C5ES chip. 

 I need the csv pin assignment file for this board. Looking in all Altera site I didn´t find this file.   The link https://www.altera.com/support/literature/lit-dp.html only supplies a .xls file for the FPGA pin description for the device, but not for the development board.  This .csv file did not came with the kit for installation DVDs of the board.  So, if someone knows how to get this file I would appreciate. Otherwise I would have to (which I won´t!) manually build a csv file through looking at the schematic file for the hundreds of pin connections.  For instance, with Terasic/DE1, a simple googling of "DE1_pin_assignments.csv" gives me hundreds of available records to download it. 

[Altera_Forum]

Did the kit DVD come with any example projects, where you can pull the pin assignments from the .qsf file or .tcl script and generate your .csv from that? 

Alternatively, you could use the tables in the reference manual and just copy&paste them with some reformatting to create your .csv file.

[Altera_Forum]

--- Quote Start ---  Did the kit DVD come with any example projects, where you can pull the pin assignments from the .qsf file or .tcl script and generate your .csv from that? Alternatively, you could use the tables in the reference manual and just copy&paste them with some reformatting to create your .csv file.  --- Quote End ---     

• <old path>\kits\kits\nios2\examples\vhdl\niosII_stratixII_2s60_ES\standard\standard.qsf opened at my quartus 13.0sp1/Windows 7/64-bit; 
• project compiled; 
• netlist Pin Planner exported for standard.csv; 
• done...  
• thank you!