时钟使用的时全局时钟输入引脚clk[xx]_2K，然后输入引脚时带cdr功能的引脚，编译出现Error: SDC cannot find the PLL that drives DPA. Clock settings of channel 0 are not created. Please check the PLL to LVDS IP connectivity.
We looked at the design and the issue seems to be from the generated SDC file of the LVDS SERDES IP. We created a standalone LVDS SERDES design with the same setting as your design does, and we don't see such error exist.
Few things we want to point out:
1. there are unconstraint clocks in the design, though those unconstraint clocks don't seem related to this issue after we fixed them.
2. we switched the LVDS SERDES IP from soft-CDR to RX DPA mode, and we see that this error goes away.
3. We created a simple design with just the LVDS SERDES IP with all the similar setting, and we don't see this error happened. We compare the generated SDC file with the one in your design, and both SDC files are the same.
1. Do you upgrade the IP which is generated from other Quartus version? From the Quartus setting file, we saw that the original Quartus version was 17.1.
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不好意思，现在才回复您，目前这个问题Error: SDC cannot find the PLL that drives DPA. Clock settings of channel 0 are not created. Please check the PLL to LVDS IP connectivity. 是在外部PLL情况下使用的出现的，你给的那个内部PLL的确没有这个问题。
但是，我现在需要使用外部PLL，我查阅lvds相关手册，有说明在使用外部PLL时，需要在SDC文件中添加 derive_pll_clocks -create_base_clocks 这一句话，但是我不知道怎么去建立一个SDC文件。您这边可以帮忙看一下吗，我一会上传一下我现在的工程。