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smile123
Beginner
80 Views

cyclone 10gx-lvds_cdr

在使用10cx220YU484芯片仿真时,使用lvds_serdes的ip核配置rx_cdr功能,内部pll模式。

时钟使用的时全局时钟输入引脚clk[xx]_2K,然后输入引脚时带cdr功能的引脚,编译出现Error: SDC cannot find the PLL that drives DPA. Clock settings of channel 0 are not created. Please check the PLL to LVDS IP connectivity. 

上面时钟输入和数据输入都是lvds标准,都处于2K Bank,希望可以得到解答。

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2 Replies
EngWei_O_Intel
Employee
58 Views

Hi

 

Can you share with us a sample design that is causing the issue? 

 

Thanks.

Eng Wei

smile123
Beginner
39 Views

您好,不好意思,现在才看到您的回复,下面这个是我用20.1_pro的软件建立的工程,非常期待您的解答。

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