cyclone III starter board DDR-SDRAM

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

cyclone III starter board DDR-SDRAM

967 Views

I am using the cyclone III starter board. I am trying to implement DDR-SDRAM with the Nios II processor. Once I developed the system with all

required components, I compiled the SOPC and added the processor system as a block in the block diagram file. Then I ran the analysis and elaboration. It shows that there are several unconnected pins.

1. How can I connect the correct pins because they do not exactly correspond with the pins given in the user manual of the board.

2. How can I set the timer for DDR-SDRAM in Nios.

3. If possible can someone give me a reference to a working exampe with the same.

Please answer what ever you can. Thanks in advance.

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.