hello everyone,when i assigned pins for my ddr design (cyclone 3 starter kit board) and did full compilation of the design the following error ocured. Error: Can't place pin ddr_dataio_dq to location V6 Error: Can't place VREF pin T6 (VREFGROUP_B3_N0) for pin ddr_dataio_dq of type bi-directional with SSTL-2 Class I I/O standard at location V6 Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin T6 (VREFGROUP_B3_N0) is used on device EP3C25F324C6 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out pin assignments are attached herewith; if i comment out the address4 pin assignment the full cmpilation succeeds. Any body got a solution for this? :confused: thank you, randeel.
Apparently, you didn't import all Megawizard generated pin setting to your design. Particularly, I don't see any OUTPUT_ENABLE_GROUP entries. They are necessary to tell the fitter, that all DQS, DQ and DM pins are sharing one output enable group and none of these pins is receiving while another drives out.