cyloneIII board questions

[Altera_Forum]

hi. 

maybe the reason of DDR SDRAM is different from the  SDRAM,I often meet the question,that is: Downloading 02000000 ( 0%) Downloading 02007E18 (78%) Downloaded 32KB in 0.5s (64.0KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2006367 Leaving target processor paused    when I run the demo or develop my own project based on the demo,there is no problem,but if I make the SOPC system on my own,the problem will be generated,but the quartusII can compile successfully...    somebody say timing requirements should meet,but the quartusII compiles ok and there is no critical warning...      and the error" cannot place pin mem_dqs[1] to location T8" often generate while compiling quartusII project when I donnot use the demo backround.    the questions puzzle me for a very long time ,can somebody help me how to resolve them???   thanks!~

[Altera_Forum]

--- Quote Start ---   maybe the reason of DDR SDRAM is different from the SDRAM (...)  and the error" cannot place pin mem_dqs[1] to location T8" often generate while compiling quartusII project when I donnot use the demo backround.    --- Quote End ---   DDR is actually different from sdr SDRAM. In particular, with SDRAM you can't freely place signals on pins but you must follow some constraints on ddr signals pin location. This could explain the error with dqs signal on pin T8. Anyway I'm missing some point: you refer to a demo project, so I suppose you are using a demo board and not a custom board. Is this your case? If yes, then the pin connection should already be correct. What C3 device are you using? Maybe you have wrongly set T8 for an alternate function: verify this in Quartus device settings.

[Altera_Forum]

I use the development board,and use the project demo which altera provides.and I am disppointed that the project which run OK,sometimes will generate "Verify failed between address" 

 maybe the ddr sdram chip on the board is bad after download projects so much times??   thanks~

[Altera_Forum]

A ddr ram doesn't degrade when reading data from and writing to, unlike a flash eprom. The only possibility is that the board was defective from the beginning (bad component or bad soldering). 

Do you use a precompiled .sof file for configuring the fpga for the demo project or did you recompile the demo project. In the first case the above hardware problem is the only plausible choice. In the second case you probably have some bad compilation setting in Quartus.

[Altera_Forum]

when I change a computer,and running the same project which gives the error,and I am suprised to find that the project runs ok. 

it is weird,and maybe because of the virus of the computer or the software bugs.

[Altera_Forum]

What do you mean with "running" the project? I think you have rebuilt it from scratch and not simply reloaded the .sof file, otherwise it would not make sense. 

This means that the former computer has something wrong with installation, project settings or maybe that computer has limited memory resources and can't make an optimal fpga fitting.

[Altera_Forum]

yes ,"run" means compile from SOPC system to the whole quartusII system. 

 this problem is still puzzling me ...        now ,I think of another question,that is :I want to set memory initialization file (.hex) of on_chip_memory ,and then use a SGDMA to get data from the memory,I add the data in .hex manually(how to add data into the .hex file automatically??) in quartusII,  but when I open the file in the form of .txt, and find that the data in the .txt is very different??  is the .hex data not only contain the useful data but also the head data or somthing?how to add data into the .hex file automatically??    if I want to add data of a picture in the on_chip_memory,how to translate the picture into .hex file then can be added in quartusII ??