de10-nano (cyclone V) - FPGA read and write from HPS SDRAM - need general direction

[zangman]

I would like to access the DDR SDRAM on the HPS from the FPGA fabric. I know I can enable it in the HPS component in Platform Designer and it shows `f2h_sdram0_data` as an Avalon Memory Mapped Slave.

What approach do I need to take to access this data? Do I need to write my own Avalon Memory Mapped Master to read the data? Or can I just export `f2h_sdram0_data` and use it directly in my verilog design?

[AnilErinch_A_Intel]

Hi ,

You can see the below thread to understand better how the data can be accessed .

https://forum.rocketboards.org/t/hps-fpga-ddr-sharing-on-cyclone-v-soc/1454/4

Thanks and Regards

Anil

[zangman · Accepted solution]

Thanks Anil! I was really in the dark as I didn't know where to begin. After a fair bit of research, I figured out what is needed:

• We need to enable the f2h_sdram0_data in the HPS in platform designer. This interface includes Avalon Slaves with the Burst interface
• Create an Avalon MM Master that supports burst interface to interact with the SDRAM
• Regarding DMA: A DMA is used to save CPU cycles by moving memory from one location to another. It's not needed for my requirements as I just want to access something in SDRAM and do something immediately with it.

I started documenting all the steps in great detail at the link below. It's still a WIP but hopefully will  be able to finish it soon and somebody new to SoCs (like myself) will find it useful:

https://github.com/zangman/de10-nano/wiki/FPGA-SDRAM-Communication:-Introduction

[AnilErinch_A_Intel]

Hi Zangman,

Good to know that your issue is resolved and thanks for sharing the solution with the community.

Thanks and Regards

Anil