FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

designware pll

jaylong
Novice
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I've used the PLL IP in Quartus and now I want to implement a similar design using the DesignWare IP. Currently, I've only found the DW_dpll_sd IP. I'd like to ask if it's also capable of producing a clock with an adjustable phase?   

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AqidAyman_Intel
Employee
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Hi,


I afraid it is beyond my capabilities to answer this question as it is related to the external IP. Let' see if we can get any input from other communities' member who has knowledge on this.


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AqidAyman_Intel
Employee
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As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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