FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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development kits DRAM upgrade errors

Honored Contributor II


I recently upgrated my quartus 9.0's project from Cyclone II de1 to stratix II dev kit. 

I'm using the NIOS processor in my project . 

my NIOS memory is a DRAM, which worked fine on the DE1 when it was connected, 


but for somehow I cant get my stratix II sdram to work. 


I get the "verify failed" massage about the sdram addresses. 


In addition I cant connect the PLL to the SOPC,but I get compilation errors about the pll. 

it only works when I connect the PLL from outside the SOPC builder. 


I know that timing is importent to the SDRAM. 


I know that I need to do phase shifting to the clk, but it still doesn't work. 


If someone had this problem and it was solved, I would like to know how. 


thanks alot, 

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