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Altera_Forum
Honored Contributor I
751 Views

devkit startix5 pcie-demo issue

Hi all, 

 

i tried to run demo pcie example that shipped with kit but it stall at ltssm: detect.Active !! , i know that was issue at ACDS less than 12 , but i'm using 13  

 

the example provided use hard IP pcie with X8 and gen2 , Avalon_st as application and print out link state and on board LED . 

 

have anyone face such issue ? 

 

thanks, 

Amr
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4 Replies
Altera_Forum
Honored Contributor I
47 Views

do you re-generate pcie-core? 

 

 

--- Quote Start ---  

Hi all, 

 

i tried to run demo pcie example that shipped with kit but it stall at ltssm: detect.Active !! , i know that was issue at ACDS less than 12 , but i'm using 13  

 

the example provided use hard IP pcie with X8 and gen2 , Avalon_st as application and print out link state and on board LED . 

 

have anyone face such issue ? 

 

thanks, 

Amr 

--- Quote End ---  

Altera_Forum
Honored Contributor I
47 Views

yes i generated another one with same connection of example ,but i've figure out problem cause : 

 

we must set test_in[5] = 0;  

to allow pcie enter compliance mode  

 

 

the another issue now that Ltssm stall at Polling.Compliance(3) state !! 

 

i doubt that the cause of this problem from either "reconfig_xcvr_clk" as it set to 125MHz and have timeQuest -ve slack or "I\O pin standard" as it silghtly different from rerferance manul of kit 

 

thanks,
Altera_Forum
Honored Contributor I
47 Views

I am having a similar issue with the Cyclone IV devkit. I have set test_in to be 40'h88, and on certain ports of my Dell computer the board stalls on the LTSSM state "Polling.Compliance". 

 

Any help would be appreciated.
Altera_Forum
Honored Contributor I
47 Views

this values of test_in that make my dev kit run successful training: 

test_in[4:0] = 5'b01000; 

test_in[5] = 0; 

test_in[31:6] = 26'h2; 

 

and please make sure of pcie lane switch of your kit . it should match your design's lanes. 

 

thanks, 

Amr
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