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fft_ip核仿真,接口时序问题

pp
New Contributor I
493 Views

我使用的软件版本是2018.1 pro专业版

在对FFT IP核进行仿真时,对其时序产生疑问,请各位帮我看看,我输入的信号时序,哪里给错了,为何输出的source_error会给2b'11的值

pp_0-1609393993469.png

pp_1-1609394044703.png

IP核的配置如下

pp_2-1609394086730.png

pp_3-1609394100049.png

 

请求帮忙,卡了好久了,实在不知道哪里出了问题

 

 

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9 Replies
CheePin_C_Intel
Employee
464 Views

Hi,

As I understand it, you observe some issue when trying to simulate with FFT IP. For your information, I have generated the example test bench using Q17.0Std mimic your IP configuration. I am able to run the simulation without error. I have attached the simulation files for your reference. You can try to look into it and cross check with yours to see if can spot any anomaly.

To run the simulation:

1. Open Modelsim and change directory to simulation_scripts\mentor

2. "source msim_setup.tcl"

3. "ld"

4. "do wave.do"

5. "run -all"

Please let me know if there is any concern. Thank you.

pp
New Contributor I
460 Views

谢谢您的解答,我先下载您的附件,先测试一下,如有任何问题或者结果,我都会回复您

pp
New Contributor I
447 Views

前辈您好,您给的例程,我已经进行仿真了,下图是您的仿真波形

pp_0-1609848353299.png

pp_1-1609848371105.png

 

接下来是我的工程的仿真波形

pp_2-1609848394527.png

pp_3-1609848415926.png

 

我没有看出有何不同呢,前辈,您能否帮我看看,指点我一下

 

CheePin_C_Intel
Employee
443 Views

Hi,


I notice that from your screenshot, when the sink_sop & sink_valid = 1, the sink_real = 0x0. Just to check with you if your first input data is 0x0 or 0x1fd511fa?


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin



pp
New Contributor I
437 Views

您好:

     sink_sop & sink_valid = 1,sink_real = 0x0是对的,我是用Matlab生成了一段正弦波,然后直接导出数据,用testbench写入的

CheePin_C_Intel
Employee
431 Views

Hi,


Thanks for your update and clarification. I raise the inquiry because I see only the first sample is 0 vs the rest in the FFT.


For your information, to facilitate further debugging, the following are things that you could look into:


1. Try with smaller size of FFT instead of the 4K FFT to ease the debugging


2. Try with fixed point instead of floating point representation just to avoid any data format issue.


3. It is recommended for you to cross check the msim_setup.tcl my shared example design with yours to ensure all the required files were compiled in your simulation. Missing files might lead to unexpected simulation behaviour.


4. To check on the data integrity, you may try to replace the data from my shared design into your test bench to see if there is any difference. The following are the details of source test data files:


i. fft_ii_0_example_design_blksize_report.txt - indicate the different FFT sizes for the test bench

ii. fft_ii_0_example_design_imag_input.txt - imag input for test bench. Set to all 0's.

iii. fft_ii_0_example_design_inverse_report.txt - FFT or iFFT control for each FFT

iv. fft_ii_0_example_design_real_input.txt - real input for test bench. The total samples (7680) tallies with the total FFT size in blksize .txt.


5. Alternatively, you can also replace your test data into the real_input.txt in #4 to try the example design. For example, replacing your 4096 samples to line1 to line4096 in real_input.txt


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin


pp
New Contributor I
428 Views

收到,如有新的进展,便回复您

CheePin_C_Intel
Employee
399 Views

Hi,

Just to follow up with you on this. Thank you.

CheePin_C_Intel
Employee
380 Views

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.



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