FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5931 Discussions

finding difficulty in porting dsign from ArriaII dev board to Cylone IV dev board

Altera_Forum
Honored Contributor II
‎10-26-2012 11:23 AM
952 Views

hey guys, 

I am trying to port a design consisting a TSE core from arria 2 dev board to cyclone 4 dev board. The design is just a loopback from a system to board and back to the system. In promiscuous mode. the design works fine in arria 2 board but not responding on cyclone 4 board. 

 

In arria 2 the design is working but signal tap is not showing the action on the IP core signals (like ff_tx_data or ff_rx_data etc). 

 

any suggestions ... 

 

thanks...
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.