01-19-2011 07:41 AM
Hi,I'm implementing a MAC for a Cyclone III 3c120 Board in VHDL. It's PHY has an RGMII inferface but can be used for 10/100 MB speeds aswell. My state machine tells me that it's written to the control register and that it reads "link is up" on the status register of the PHY. But the connection to my PC doesn't seem to be set up and the "100MB LED" isn't on either. This is what I'm writing onto the MDIO: ... shiftreg <= "01" & "01" & phy_address & mi_cmd_type(4 downto 0) & "00"; ... I'm not sure if I'm writing to the correct PHY address! I don't know what it's hardcoded to. How can I find out what PHY address my chip has? The reference manuel doesn't tell me anything.
01-19-2011 08:59 AM
You can have a look at the schematic, or do as the Interniche driver does, i.e. try all the PHY addresses until you get an answer.You shouldn't have to force the PHY chip into any mode, if your PC is limited to 100Mbits/s the PHY chip should detect it during autonegotiation and switch automatically to 100Mbits/s mode. IIRC the Marvel chip needs to be properly taken out of reset or it will behave strangely. Check that you provide a nice reset pulse to the chip during initialization, and have a look at the Interniche driver to see how it should be initialized through the MDIO registers after reset.
02-14-2011 09:50 AM
Thanks for that answer! It works when I force my PC network card to 100MBit/s.I've read the Marvell data sheet and I've sent a reset pulse and what you need to set the PHY control register. However, I still can't read from the PHY. Don't exactly know where to look for the Iniche Code, but I've left the PHY in autoneg. and setting my PC to 100MB does the job. I've written a windows socket application (winsock) to receive the UDP packets which I'm sending from the FPGA. However, there seems to be a problem (maybe with my firewall). Because it only detects the packets when I start a wireshark capture! I know this might not be the right forum for that question, but maybe someone can help me on that??