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fpga to hps bridge - stratix 10

james57
New Contributor I
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Hi all,

 

Currently I am working on understanding the HPS-FPGA bridges on the Stratix 10. I have been able to write from the hps to fpga peripherals using the LW bridge. I am now trying to send data from the FPGA using the complete bridge, do some arithmetic, and then send the result back top the HPS, esentially just a loopback. I have been updated the top level qsys file to have two bridges and an arithmetic block between the two. This has not worked however because I am unsure what the address and address offset for the f2h slave is. I am not sure what I am missing, or even if my hardware is being programmed properly for that matter.

I will attach a photo of my current qsys design.

 

Any help for this project would be much appreciated.

 

Thanks

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JingyangTeh
Employee
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Hi James


Sorry for the late reply, there was a long weekend in my region.


For building the hardware design, you do not need to run the yocto build all the time.

It is meant for building the rootfs for the linux OS.

If there is not changes to the linux portion you could skip the linux building part and only run only the relevant steps.


Regards

Jingyang, Teh



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JingyangTeh
Employee
1,615 Views

Hi James

 

You could see a list of the address offset under the "Address Map" tab.

Refer to the picture below:

 

 

2023-06-23_09h15_24.png

For example the button_pio.s1 via mm_bridge_0.

You will go under the column of the hps.

In the picture you can see it is connected to the hps_h2f_lw bridge. with the offset of 0x600c0.

You would need to go the Address Map of the device and search for the start address for the hps_h2f_lw_bridge.

In this case it is a Cyclone V device the start address of the hps_h2f_lw_bridge is 0xFF200000. (refer to cyclone V Address Map https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html)

 

From HPS the address of the button_pio.s1 via mm_bridge_0 will be 0xFF2600c0.

 

 

 

For your case you would refer to the Stratix10 Address map :

https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html

 

 

Regards

Jingyang, Teh

 

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james57
New Contributor I
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Hi @JingyangTeh 

 

Thank you for the help! I have been able to get the h2f_lw bridge working! My real issue is using the f2h bridge.

I have updated my Qsys design based off of this reference I found from Cornell University:

https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_peripherials/FPGA_addr_index.html

Specifically

https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_FPGA/FIFO/FIFO_write_read/Qsys.PNG

 

I will attach my design as well.

updated-Qsys.png

And here are my address maps

address-map.png

After generating the HDL and adding in a simple function into the verilog file

 

"

always @(posedge clk_100_out_clk_clk or posedge rst_controller_reset_out_reset) begin
if (rst_controller_reset_out_reset) begin
internal_reg <= 0;
end else begin
// Perform arithmetic (multiply by 10)
internal_reg <= qsys_top_fifo_hps_to_fpga_out_csr_writedata * 10;
end
end

assign qsys_top_fifo_fpga_to_hps_in_csr_writedata = internal_reg;

"

 

I have developed C code for a server and a client socket.  Here are some important parts

" Server.c

#define FPGA_BASE_ADDRESS 0xF9000000 // BASE ADDRESS For MASTER
#define FPGA_SPAN 0x00200000 // 2 MB Span

#define INPUT_REG_OFFSET 0x20 // BASE ADDRESS for input reg
#define OUTPUT_REG_OFFSET 0x00 // BASE ADDRESS for output reg

...

// Map the FPGA AXI slave interface to the virtual address space
void *virtual_base = mmap(NULL, FPGA_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, fd, FPGA_BASE_ADDRESS);
if (read == MAP_FAILED) {
perror("Failed to map memory");
close(fd);
return -1;
}

// Get the virtual address of the input and output registers
volatile uint32_t *input_reg = (volatile uint32_t *)(virtual_base + INPUT_REG_OFFSET);
volatile uint32_t *output_reg = (volatile uint32_t *)(virtual_base + OUTPUT_REG_OFFSET);

...

// Receive data from the client
int valread = recv(new_socket, buffer, sizeof(buffer), 0);
if (valread <= 0) {
perror("recv failed");
break;
}

if (strcmp(buffer, "Exit\n") == 0) {
// Exit the arithmetic
printf("Exiting...\n");
break;
} else {
sscanf(buffer, "%ls", &value);
// valid input

printf("Client Input: %ls\n", &value);

*input_reg = value;

// Wait for the FPGA to perform the arithmetic
usleep(1000);

// Read the result from the FPGA
result = *output_reg;

"

 

And for the client

 

" client.c

...

// Receive the server's response
memset(buffer, 0, sizeof(buffer));
rec = read(sock, &rec, sizeof(rec));
printf("Server response: %d\n", rec);
rec = 0;
}

"

 

Here is the output.

 

Client Output:

client-output.png

Server Output:

server-output.png

The server can see the correct input from the client, however the result is a constant "2899692286", which is curious because this is the output from the command

root@stratix10:~# cat /sys/bus/platform/devices/f9000000.SYSID_QSYS/sysid/id

 found in https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForStratix10SoC

 

and the client collects a constant "4" which is also strange because I would expect that it would return "2899692286".

This leads me to believe that the fpga to hps bridge is not configured correctly, or I have put the wrong address for OUTPUT_REG in my c code, which is why I have bolded it. I am confident though that the h2f_lw bridge is working.

 

The Output should just multiply the input by 10, not this system ID.

 

Sorry about the overflow of information.

Again, any help to understand the f2h bridge would be very helpful.

 

Thanks,

James

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james57
New Contributor I
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Hi @JingyangTeh 

 

I wrote you a response this morning but it did not seem to get posted.

Thank you for the response. My issue is not with the HPS to FPGA transaction it is with the FPGA to HPS Bridge. I have updated my QSYS design to be the following:

updated-Qsys.png

address-map.png

and have added a little verilog function

 

always @(posedge clk_100_out_clk_clk or posedge rst_controller_reset_out_reset) begin
if (rst_controller_reset_out_reset) begin
internal_reg <= 0;
end else begin
// Perform arithmetic (multiply by 10)
internal_reg <= mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata * 10;
end
end

assign mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata = internal_reg;

 

Simply taking the input multiplying it by ten and sending it to another fifo. My C programs have the following headings...

 

#define FPGA_BASE_ADDRESS 0xF9000000 // BASE ADDRESS For MASTER
#define FPGA_SPAN 0x00200000 // 2 MB Span

#define INPUT_REG_OFFSET 0x20 // BASE ADDRESS for input reg
#define OUTPUT_REG_OFFSET 0x00 // BASE ADDRESS for output reg

 

And the outputs show this.

server-output.png

client-output.png

I am getting information across.

 

I am not sure what is going on. any help with the f2h bridge would be so much help!

 

Thanks,

James

 

 

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JingyangTeh
Employee
1,525 Views

Hi James


Sorry for the late reply.


Here is what I could gather.

Using the FPGA to HPS bridge you will be accessing the DDR of the HPS.

The addressing will be base on the DDR size :

https://www.intel.com/content/www/us/en/docs/programmable/683222/22-4/example-recommended-system-memory-mapping.html


Unfortunately, there is no design example for the FPGA to HPS bridge for the Stratix10.

However there is an example for the Arria10 board:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html


Regards

Jingyang, Teh



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james57
New Contributor I
1,511 Views

Hi @JingyangTeh 

 

Thank you for looking into this for me.

 

I have a suspicion that the reason my design is not working is because the "Address Map" for my design is not being exported onto the board.

 

There is a good chance I am programming the board wrong - or incorrectly making the device tree.

 

What is the proper way to program the Stratix 10 Board with my developed hardware design?

 

I ask because I am unable to use the Quartus Programmer without losing terminal control of the board. 

 

Thanks,

 

James

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JingyangTeh
Employee
1,476 Views

Hi James


What do you mean losing terminal control of your board? Are you referring that the board will power cycle during and after the programming phase? If so it is expected.


You could refer to the link below on the steps of flashing the board.

Please pay attention to the MSEL selection switch during programming.

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10#Boot_Linux


Regards

Jingyang, Teh


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JingyangTeh
Employee
1,444 Views

Hi James


Any update on this case?

Are you still facing problem with the flashing?


Regards

Jingyang, Teh


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james57
New Contributor I
1,431 Views

HI @JingyangTeh 

 

I have been able to boot my desired hardware design on the board now after following the link you provided -

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10#Boot_Linux

I appreciate the help.

 

I am curious if I have to follow these steps all the way through if I change the hardware design (building yocto each time is slow on my machine) or if there is an easier path.

 

Thanks,

James

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JingyangTeh
Employee
1,357 Views

Hi James


Sorry for the late reply, there was a long weekend in my region.


For building the hardware design, you do not need to run the yocto build all the time.

It is meant for building the rootfs for the linux OS.

If there is not changes to the linux portion you could skip the linux building part and only run only the relevant steps.


Regards

Jingyang, Teh



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JingyangTeh
Employee
1,297 Views

Hi James


Any update on this case?


Regards

Jingyang, Teh


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james57
New Contributor I
1,282 Views

Hi @JingyangTeh 

 

I believe I have resolved my issue and understand what I was doing wrong, thank you for the help!

 

James

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JingyangTeh
Employee
1,270 Views

Hi


Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


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