Link Copied
Hi James
You could see a list of the address offset under the "Address Map" tab.
Refer to the picture below:
For example the button_pio.s1 via mm_bridge_0.
You will go under the column of the hps.
In the picture you can see it is connected to the hps_h2f_lw bridge. with the offset of 0x600c0.
You would need to go the Address Map of the device and search for the start address for the hps_h2f_lw_bridge.
In this case it is a Cyclone V device the start address of the hps_h2f_lw_bridge is 0xFF200000. (refer to cyclone V Address Map https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html)
From HPS the address of the button_pio.s1 via mm_bridge_0 will be 0xFF2600c0.
For your case you would refer to the Stratix10 Address map :
https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html
Regards
Jingyang, Teh
Hi @JingyangTeh
Thank you for the help! I have been able to get the h2f_lw bridge working! My real issue is using the f2h bridge.
I have updated my Qsys design based off of this reference I found from Cornell University:
https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_peripherials/FPGA_addr_index.html
Specifically
https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/HPS_FPGA/FIFO/FIFO_write_read/Qsys.PNG
I will attach my design as well.
And here are my address maps
After generating the HDL and adding in a simple function into the verilog file
"
always @(posedge clk_100_out_clk_clk or posedge rst_controller_reset_out_reset) begin
if (rst_controller_reset_out_reset) begin
internal_reg <= 0;
end else begin
// Perform arithmetic (multiply by 10)
internal_reg <= qsys_top_fifo_hps_to_fpga_out_csr_writedata * 10;
end
end
assign qsys_top_fifo_fpga_to_hps_in_csr_writedata = internal_reg;
"
I have developed C code for a server and a client socket. Here are some important parts
" Server.c
#define FPGA_BASE_ADDRESS 0xF9000000 // BASE ADDRESS For MASTER
#define FPGA_SPAN 0x00200000 // 2 MB Span
#define INPUT_REG_OFFSET 0x20 // BASE ADDRESS for input reg
#define OUTPUT_REG_OFFSET 0x00 // BASE ADDRESS for output reg
...
// Map the FPGA AXI slave interface to the virtual address space
void *virtual_base = mmap(NULL, FPGA_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, fd, FPGA_BASE_ADDRESS);
if (read == MAP_FAILED) {
perror("Failed to map memory");
close(fd);
return -1;
}
// Get the virtual address of the input and output registers
volatile uint32_t *input_reg = (volatile uint32_t *)(virtual_base + INPUT_REG_OFFSET);
volatile uint32_t *output_reg = (volatile uint32_t *)(virtual_base + OUTPUT_REG_OFFSET);
...
// Receive data from the client
int valread = recv(new_socket, buffer, sizeof(buffer), 0);
if (valread <= 0) {
perror("recv failed");
break;
}
if (strcmp(buffer, "Exit\n") == 0) {
// Exit the arithmetic
printf("Exiting...\n");
break;
} else {
sscanf(buffer, "%ls", &value);
// valid input
printf("Client Input: %ls\n", &value);
*input_reg = value;
// Wait for the FPGA to perform the arithmetic
usleep(1000);
// Read the result from the FPGA
result = *output_reg;
"
And for the client
" client.c
...
// Receive the server's response
memset(buffer, 0, sizeof(buffer));
rec = read(sock, &rec, sizeof(rec));
printf("Server response: %d\n", rec);
rec = 0;
}
"
Here is the output.
Client Output:
Server Output:
The server can see the correct input from the client, however the result is a constant "2899692286", which is curious because this is the output from the command
root@stratix10:~# cat /sys/bus/platform/devices/f9000000.SYSID_QSYS/sysid/id
found in https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForStratix10SoC
and the client collects a constant "4" which is also strange because I would expect that it would return "2899692286".
This leads me to believe that the fpga to hps bridge is not configured correctly, or I have put the wrong address for OUTPUT_REG in my c code, which is why I have bolded it. I am confident though that the h2f_lw bridge is working.
The Output should just multiply the input by 10, not this system ID.
Sorry about the overflow of information.
Again, any help to understand the f2h bridge would be very helpful.
Thanks,
James
Hi @JingyangTeh
I wrote you a response this morning but it did not seem to get posted.
Thank you for the response. My issue is not with the HPS to FPGA transaction it is with the FPGA to HPS Bridge. I have updated my QSYS design to be the following:
and have added a little verilog function
always @(posedge clk_100_out_clk_clk or posedge rst_controller_reset_out_reset) begin
if (rst_controller_reset_out_reset) begin
internal_reg <= 0;
end else begin
// Perform arithmetic (multiply by 10)
internal_reg <= mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata * 10;
end
end
assign mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata = internal_reg;
Simply taking the input multiplying it by ten and sending it to another fifo. My C programs have the following headings...
#define FPGA_BASE_ADDRESS 0xF9000000 // BASE ADDRESS For MASTER
#define FPGA_SPAN 0x00200000 // 2 MB Span
#define INPUT_REG_OFFSET 0x20 // BASE ADDRESS for input reg
#define OUTPUT_REG_OFFSET 0x00 // BASE ADDRESS for output reg
And the outputs show this.
I am getting information across.
I am not sure what is going on. any help with the f2h bridge would be so much help!
Thanks,
James
