full constraints file for the Arria 10 PAC

[druva1]

Hi,

I have in my pc (windows) an Arria 10 PAC. I would like to program it with Quartus Prime Pro as a normal FPGA and not use the Acceleration Stack for Intel or AFU.

I am searching for the full constraints file for the board and the pinout (clocks and PCIe ports location) of the board so I can test a small PCIe example.

I appreciate the help, thanks.

[EricMunYew_C_Intel]

Hi, the info you request is not available and it is confidential, as the Arria 10 PAC card is created for acceleration platform and flow.

[druva1 · Accepted solution]

It is ok, thanks.