FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5145 Discussions

how can I find the SDI II Transceiver reconfiguration register(address = 0x0E)

CWei10
Beginner
1,126 Views

I'm using a chip C5GXFC5F6M11C6 to make a FPGA design With SDI II IP.

In order to implement reconfiguration management(user logic), I reference the SDI II example design which is generated when I parameterized the SDI II Intel FPGA IP core and checked the "Generate Example Design" option.

In the example design there is a sdi_ii_reconfig_logic.v for reconfiguration management.

And in the sdi_ii_reconfig_logic.v file there is a in the "SET_OFFSET" state and the "wdata <= reg_offset;" is for write a offset value 0x0000000E("RX_OFFSET_M_L_COUNTER = 4'he") to Transceiver Reconfiguariton Controller.

In [SDI II Intel® FPGA IP User Guide] I foud the information as attached picture image, The offset 0X0000000E is a address point to a register in the transceiver.

table 17_24.png

I searched the 「V-Series Transceiver PHY IP Core User Guide」and 「Cyclone V Device Handbook Volume 2: Transceivers」, But I didn't find a register description which address is 0X0000000E.

Could you teach me how can I find this register description?

0 Kudos
2 Replies
CheePin_C_Intel
Employee
124 Views

Hi CWei10,

 

If I understand it correctly, you are referring to the RX_OFFSET_M_L_COUNTER register inside the sdi_ii_reconfig_logic.v. Yes, you are right, this register seems not available in the XCVR PHY user guide. As I understand it, these seems to be some internal registers which is not available to user by default. When the SDI IP is perform the reconfiguration, it is accessing these internal registers to update the parameter.

 

Sorry for the inconvenience.

 

Chee Pin

CWei10
Beginner
124 Views

I understand that detailed definition of the RX_OFFSET_M_SEL register inside the Transceiver PHY is not made public to the user.

Thank you very much for your detailed answer.

Reply