how can i know the type of input in ethernet generated from pluggin for VHDL to define variable?and find that there are two reserved words in ethernet's file, one is read, another is write, what should i pass to them when a testing TX or RX? when making a VHDL testing bench to test TX and RX data to my home computer, any other button in menu i should click? or i just need to create a simple top layer VHDL file, then it can run as i find test bench AN585 has tcl and Verilog, when search ff_tx_data, i do not find any data it passed to ethernet to transmit. How can it test?
i confused about writedata in MAC control interface and ff_tx_data in transmit interface, what to assign to them? i guess at least one be assigned the data transmittedis it higher frequency clk in MAC control interface result in faster speed? if using 1000Mb speed, how many clock frequency should use?
writedata and ff_tx_data are part of two different interfaces. writedata is part of an Avalon Memory Mapped interface, used to configure the MAC registers, while ff_tx_data is the Avalon Stream interface used to send actual packets. The clocked used on the PHY side depends on the interface between the MAC and the PHY and needs to be precise. The clock used on the avalon side should just be at least fast enough to support the bandwidth.